K40P81M100SF2_11 Datasheet, PDF (25/63 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Peripheral operating requirements and behaviors
Table 13. MCG specifications (continued)
Symbol Description
Min.
f_{dco_t_DMX3} DCO output
2
frequency
Low range (DRS=00)
—
732 × f_{fll_ref}
Mid range (DRS=01)
—
1464 × f_{fll_ref}
Mid-high range (DRS=10)
—
2197 × f_{fll_ref}
High range (DRS=11)
—
2929 × f_{fll_ref}
J_{cyc_fll} FLL period jitter
—
J_{acc_fll} FLL accumulated jitter of DCO output over a 1µs
—
time window
t_{fll_acquire} FLL target frequency acquisition time
—
PLL
f_vco
VCO operating frequency
48.0
I_pll
PLL operating current
• PLL @ 96 MHz (f_{osc_hi_1}=8MHz,
—
f_{pll_ref}=2MHz, VDIV multiplier=48)
f_{pll_ref} PLL reference frequency range
2.0
J_{cyc_pll} PLL period jitter
—
J_{acc_pll} PLL accumulated jitter over 1µs window
—
D_lock Lock entry frequency tolerance
± 1.49
D_unl Lock exit frequency tolerance
± 4.47
t_{pll_lock} Lock detector detection time
—
Typ.
23.99
Max.
—
47.97
—
71.99
—
95.98
—
TBD
TBD
—
TBD
TBD
1
—
100
950
—
—
400
TBD
—
—
—
4.0
—
—
± 2.98
± 5.97
0.15 +
1075(1/
f_{pll_ref})
Unit
MHz
MHz
MHz
MHz
ps
ps
ms
MHz
µA
MHz
ps
ps
%
%
ms
Notes
4, 5
6
6
7
8
9, 10
9, 10
11
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δf_{dco_t}) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification was obtained at TBD frequency.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. This specification was obtained at internal frequency of TBD.
11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
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