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K40P81M100SF2_11 Datasheet, PDF (38/63 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
Peripheral operating requirements and behaviors
Table 26. 16-bit ADC with PGA characteristics (continued)
Symbol
THD
Description
Total harmonic
distortion
Conditions
• Gain=1
• Gain=64
Min.
Typ.1
Max.
Unit
TBD
89.4
—
dB
TBD
90.0
—
dB
SFDR
Spurious free
dynamic range
• Gain=1
• Gain=64
TBD
90.9
—
dB
TBD
77.0
—
dB
ENOB
Effective number
of bits
• Gain=1, Average=4
• Gain=1, Average=8
TBD
12.3
—
bits
TBD
12.7
—
bits
• Gain=64, Average=4
TBD
8.4
—
bits
• Gain=64, Average=8
TBD
8.7
—
bits
• Gain=1, Average=32
TBD
13.3
—
bits
• Gain=2, Average=32
TBD
13.1
—
bits
• Gain=4, Average=32
TBD
12.5
—
bits
• Gain=8, Average=32
TBD
11.8
—
bits
• Gain=16, Average=32
TBD
11.1
—
bits
• Gain=32, Average=32
TBD
10.2
—
bits
• Gain=64, Average=32
TBD
9.3
—
bits
Notes
16-bit
differential
mode,
Average=32,
fin=500Hz
16-bit
differential
mode,
Average=32,
fin=500Hz
16-bit
differential
mode,
fin=500Hz
SINAD
Signal-to-noise
plus distortion
ratio
See ENOB
6.02 × ENOB + 1.76
dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function if input common mode voltage (VCM) and the PGA gain.
3. This is the input leakage current of the module in addition to the PAD leakage current.
4. Gain = 2PGAG
5. When the PGA gain is changed, it takes some time to settle the output for the ADC to work properly. During a gain
switching, a few ADC outputs should be discarded (minimum two data samples, may be more depending on ADC
sampling rate and time of the switching).
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 27. Comparator and 6-bit DAC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDHS Supply current, High-speed mode (EN=1, PMODE=1)
—
—
200
μA
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
38
Preliminary
Freescale Semiconductor, Inc.