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K40P81M100SF2_11 Datasheet, PDF (42/63 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
Peripheral operating requirements and behaviors
6.6.3.2 12-bit DAC operating behaviors
Table 29. 12-bit DAC operating behaviors
Symbol Description
IDDA_DACLP Supply current — low-power mode
IDDA_DACH Supply current — high-speed mode
P
tDACLP Full-scale settling time (0x080 to 0xF7F) — low-
power mode
tDACHP Full-scale settling time (0x080 to 0xF7F) — high-
power mode
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) —
low-power mode
tCCDACHP Code-to-code settling time (0xBF8 to 0xC08) —
high-speed mode
Vdacoutl DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
Vdacouth DAC output voltage range high — high-speed
mode, no load, DAC set to 0xFFF
INL Integral non-linearity error — high speed mode
DNL
DNL
Differential non-linearity error — VDACR > 2 V
Differential non-linearity error — VDACR =
VREFO (1.15 V)
VOFFSET
EG
PSRR
TCO
TGE
Offset error
Gain error
Power supply rejection ratio, VDDA > = 2.4 V
Temperature coefficient offset voltage
Temperature coefficient gain error
Min.
—
—
—
—
—
1
—
VDACR
−100
—
—
—
±0.4
±0.1
60
—
—
Typ.
—
—
100
15
—
TBD
100
—
—
—
—
—
—
TBD
TBD
Max.
150
700
200
30
5
—
TBD
VDACR
±8
±1
±1
±0.8
±0.6
90
—
—
AC
Offset aging coefficient
Rop Output resistance load = 3 kΩ
SR
Slew rate -80h→ F7Fh→ 80h
• High power (SPHP)
• Low power (SPLP)
CT
Channel to channel cross talk
BW 3dB bandwidth
• High power (SPHP)
• Low power (SPLP)
—
—
TBD
—
—
250
1.2
1.7
—
0.05
0.12
—
—
—
-80
550
—
—
40
—
—
Unit
μA
μA
μs
μs
μs
μs
mV
mV
LSB
LSB
LSB
%FSR
%FSR
dB
μV/C
ppm of
FSR/C
μV/yr
Ω
V/μs
dB
kHz
Notes
1
1
1
1
2
3
4
5
5
1. Settling within ±1 LSB
2. The INL is measured for 0+100mV to VDACR−100 mV
3. The DNL is measured for 0+100 mV to VDACR−100 mV
4. The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4V
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
42
Preliminary
Freescale Semiconductor, Inc.