K40P81M100SF2_11 Datasheet, PDF (22/63 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Peripheral operating requirements and behaviors
Table 12. JTAG full voltage range electricals (continued)
Symbol
J10
J11
J12
J13
J14
Description
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
Min.
Max.
Unit
1.4
—
ns
—
22.1
ns
—
22.1
ns
100
—
ns
8
—
ns
TCLK (input)
J2
J3
J3
J4
J4
Figure 5. Test clock input timing
TCLK
Data inputs
Data outputs
Data outputs
Data outputs
J5
J6
Input data valid
J7
Output data valid
J8
J7
Output data valid
Figure 6. Boundary scan (JTAG) timing
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
22
Preliminary
Freescale Semiconductor, Inc.