K40P81M100SF2_11 Datasheet, PDF(39/63 Page) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

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K40P81M100SF2_11 Datasheet, PDF (39/63 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

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Peripheral operating requirements and behaviors

Table 27. Comparator and 6-bit DAC electrical specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

IDDLS

Supply current, low-speed mode (EN=1, PMODE=0)

Î¼A

VAIN

Analog input voltage

VSS â 0.3

VDD

VAIO

Analog input offset voltage

Analog comparator hysteresis1

â¢ CR0[HYSTCTR] = 00

â¢ CR0[HYSTCTR] = 01

â¢ CR0[HYSTCTR] = 10

â¢ CR0[HYSTCTR] = 11

VCMPOh

VCMPOl

tDHS

tDLS

IDAC6b

INL

DNL

Output high

Output low

Propagation delay, high-speed mode (EN=1,

PMODE=1)

Propagation delay, low-speed mode (EN=1,

PMODE=0)

Analog comparator initialization delay2

6-bit DAC current adder (enabled)

6-bit DAC integral non-linearity

6-bit DAC differential non-linearity

VDD â 0.5

120

250

â0.5

â0.3

0.5

200

600

TBD

0.5

0.3

Î¼A

LSB3

LSB

1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V.

2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,

VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.

3. 1 LSB = Vreference/64

K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.

Freescale Semiconductor, Inc.

Preliminary

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