K40P81M100SF2_11 Datasheet, PDF (56/63 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Pinout
8 Pinout
8.1 K40 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
The 81-pin ballmap assignments are currently being developed.
The • in the entries in this package column indicate which
signals are present on the package.
81 80 Pin Name Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
MAP LQF
BGA P
• 1 PTE0
ADC1_SE4 ADC1_SE4 PTE0
a
a
SPI1_PCS1 UART1_TX SDHC0_D1
I2C1_SDA
• 2 PTE1
ADC1_SE5 ADC1_SE5 PTE1
a
a
SPI1_SOUT UART1_RX SDHC0_D0
I2C1_SCL
• 3 PTE2
ADC1_SE6 ADC1_SE6 PTE2
a
a
SPI1_SCK UART1_CT SDHC0_DC
S_b
LK
• 4 PTE3
ADC1_SE7 ADC1_SE7 PTE3
a
a
SPI1_SIN UART1_RT SDHC0_CM
S_b
D
• 5 PTE4
DISABLED
PTE4
SPI1_PCS0 UART3_TX SDHC0_D3
• 6 PTE5
DISABLED
PTE5
SPI1_PCS2 UART3_RX SDHC0_D2
• 7 VDD
VDD
VDD
• 8 VSS
VSS
VSS
• 9 USB0_DP USB0_DP USB0_DP
• 10 USB0_DM USB0_DM USB0_DM
• 11 VOUT33 VOUT33 VOUT33
• 12 VREGIN VREGIN VREGIN
• 13 PGA0_DP/ PGA0_DP/ PGA0_DP/
ADC0_DP0/ ADC0_DP0/ ADC0_DP0/
ADC1_DP3 ADC1_DP3 ADC1_DP3
• 14 PGA0_DM/ PGA0_DM/ PGA0_DM/
ADC0_DM0/ ADC0_DM0/ ADC0_DM0/
ADC1_DM3 ADC1_DM3 ADC1_DM3
• 15 PGA1_DP/ PGA1_DP/ PGA1_DP/
ADC1_DP0/ ADC1_DP0/ ADC1_DP0/
ADC0_DP3 ADC0_DP3 ADC0_DP3
• 16 PGA1_DM/ PGA1_DM/ PGA1_DM/
ADC1_DM0/ ADC1_DM0/ ADC1_DM0/
ADC0_DM3 ADC0_DM3 ADC0_DM3
• 17 VDDA
VDDA
VDDA
EzPort
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
56
Preliminary
Freescale Semiconductor, Inc.