K40P81M100SF2_11 Datasheet, PDF (49/63 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Peripheral operating requirements and behaviors
6.8.6 DSPI switching specifications (high-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 38. Master mode DSPI timing (high-speed mode)
Num
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
Operating voltage
Description
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn to DSPI_SCK output valid
DSPI_SCK to DSPI_PCSn output hold
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Min.
2.7
—
2 x t_BCLK
(t_SCK/2) − 2
(t_SCK/2) − 2
(t_SCK/2) − 2
—
−2
TBD
0
Max.
3.6
25
—
(t_SCK/2) + 2
—
—
8.5
—
—
—
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
DS3
DS2
DS1
DS4
DS7
DS8
First data
DS5
First data
Data
Last data
DS6
Data
Last data
Num
DS9
DS10
Figure 21. DSPI classic SPI timing — master mode
Table 39. Slave mode DSPI timing (high-speed mode)
Description
Operating voltage
Frequency of operation
DSPI_SCK input cycle time
DSPI_SCK input high/low time
Min.
2.7
4 x t_BCLK
(t_SCK/2) − 2
Max.
3.6
12.5
—
(t_SCK/2 + 2
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
Unit
V
MHz
ns
ns
49