K40P81M100SF2_11 Datasheet, PDF (47/63 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Peripheral operating requirements and behaviors
Table 35. USB VREG electrical specifications
(continued)
Symbol
V_Reg33out
C_OUT
ESR
I_LIM
Description
Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
External output capacitor
External output capacitor equivalent series
resistance
Current limitation threshold
Min.
2.3
1.76
1
185
Typ.
—
2.2
—
290
Max.
3.6
8.16
100
395
Unit
Notes
V
1
μF
mΩ
mA
1. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to I_Load.
6.8.4 CAN switching specifications
See General switching specifications.
6.8.5 DSPI switching specifications (low-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 36. Master mode DSPI timing (low-speed mode)
Num
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
Operating voltage
Description
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn to DSPI_SCK output valid
DSPI_SCK to DSPI_PCSn output hold
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Min.
1.71
—
4 x t_BCLK
(t_SCK/2) - 4
(t_SCK/2) - 4
(t_SCK/2) - 4
—
-2
15
0
Max.
3.6
12.5
—
(t_SCK/2) + 4
—
—
10
—
—
—
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
47