XRT72L58 Datasheet, PDF (94/486 Pages) Exar Corporation – EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L58
REV. P1.1.2
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
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PRELIMINARY
es these additional requirements. Whereas, writing a
'0' causes the Receive DS3/E3 Framer block to waive
this requirement.
NOTE: For more information on Framing with Parity please
see Section 3.3.2.2.
Bit 1 - F Sync Algo(rithim Select)
This 'Read/Write' bit-field, in conjunction with Bits 0
and 2 of this register, allows the user to completely
define the Frame Maintenance Criteria of the Receive
DS3/E3 Framer block. This particular bit-field allows
the user to define the Frame Maintenance Criteria as
it applies to F-bits.
If the user writes a "1" to this bit-field, then the Re-
ceive DS3/E3 Framer block will declare an Out of
Frame (OOF) condition if 3 out of 16 F-Bits are in Er-
ror. If the user writes a "0" to this bit-field, then the
Receive DS3/E3 Framer block will declare an Out of
Frame (OOF) condition is 6 out of 16 F-bits are in er-
ror.
NOTE: For more information on the use of this bit, and the
Framing Maintenance operation of the Receive DS3/E3
Framer block, please see Section 3.3.2.2.
Bit 0 - M Sync Algo(rithm Select)
This 'Read/Write' bit-field in conjunction with Bits 1
and 2 of this register, allows the user to completely
define the Frame Maintenance Criteria of the Receive
DS3/E3 Framer block. This particular bit-field allows
the user to define the Frame Maintenance criteria, as
it applies to M-bits.
If the user writes a "1" to this bit-field, then the Re-
ceive DS3/E3 Framer block will declare an Out of
Frame (OOF) condition if 3 out of 4 M-bits are in error.
If the user writes a "0" to this bit-field, then the Re-
ceive DS3/E3 Framer block will ignore the occurrence
of M-bit errors while operating in the Frame Mainte-
nance mode.
NOTE: For more information on the use of this bit-field, and
the Framing Maintenance operation of the Receive DS3/E3
Framer block, please see Section 3.3.2.2.
2.4.2.9 Receive DS3 Status Register
RXDS3 STATUS REGISTER (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
RxFERF
RxAIC
RxFEBE[2:0]
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
Bit 4 - RxFERF Indicator
This Read Only bit-field indicates whether or not the
Receive Section of the channel is declaring a FERF
(Far-End-Receive Failure) condition.
If this bit-field is set to "0", then the Receive Section
(of the channel) is currently not declaring an FERF
condition.
If this bit-field is set to "1", then the Receive Section
(of the chip) is currently declaring an FERF condition.
NOTE: For more information on how the Receive Section of
the channel declares the FERF condition, please see Sec-
tion 3.3.2.5.4.
Bit 3 - RxAIC
This Read Only bit-field reflect the value of the AIC
bit-field, within the incoming DS3 Frames, as detect-
ed by the Receive DS3/E3 Framer block (within the
channel). This bit-field is set to "1" if the incoming
frame is determined to be in the C-bit Parity Format
(AIC bit = 1) for at least 63 consecutive frames. This
bit-field is set to "0" if two (2) or more M-frames, out of
the last 15 M-frames, contain a "0" in the AIC bit posi-
tion.
Bits 2:0 - RxFEBE[2:0]
These Read-Only bit-fields reflect the FEBE value,
within the most recently received DS3 frame.
If these bit-fields are set to "111", then it indicates that
the Remote Receiving Terminal is receiving DS3
frames in an un-erred manner.
If these bit-fields are set to "011", then it indicates that
the Remote Receiving Terminal has detected Fram-
ing or Parity bit errors in the DS3 frames that it is re-
ceiving.
NOTE: For more information on FEBE (Far-End-Block
Error) please see Section 3.3.2.5.5.
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