XRT72L58 Datasheet, PDF (16/486 Pages) Exar Corporation – EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L58
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
TERFACE BLOCK .................................................................................................................................... 335
Figure 150. Illustration of the Terminal Equipment being interfaced to the Receive Payload Data Input In-
terface Block of the XRT72L58 Framer IC (Serial Mode Operation) ................................................... 336
Figure 151. An Illustration of the behavior of the signals between the Receive Payload Data Output Inter-
face block of the XRT72L58 and the Terminal Equipment .................................................................. 337
Figure 152. Illustration of the XRT72L58 DS3/E3 Framer IC being interfaced to the Receive Section of the
Terminal Equipment (Nibble-Parallel Mode Operation) ....................................................................... 338
Figure 153. Illustration of the signals that are output via the Receive Payload Data Output Interface block
(for Nibble-Parallel Mode Operation). .................................................................................................. 339
5.3.6 Receive Section Interrupt Processing ................................................................................................... 339
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ...................................................................... 340
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) .................................................................. 340
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) .................................................................. 341
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ....................................................... 341
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) .................................................................. 342
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) .................................................................. 342
RXE3 CONFIGURATION & STATUS REGISTER 2 (ADDRESS = 0X11) ......................................................... 342
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) .................................................................. 343
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ....................................................... 343
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) .................................................................. 344
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ....................................................... 344
RXE3 INTERRUPT ENABLE REGISTER - 1 (ADDRESS = 0X12) ................................................................ 345
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14) .................................................................. 345
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) .................................................................. 346
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) .................................................................. 346
RXE3 CONFIGURATION & STATUS REGISTER - 2 (ADDRESS = 0X11) ....................................................... 346
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) .................................................................. 347
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) .................................................................. 347
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13) .................................................................. 348
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) .................................................................. 348
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ............................................................................ 348
RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ............................................................................ 349
6.0 E3/ITU-T G.832 Operation of the XRT72L58 ..................................................................................... 350
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 350
6.1 DESCRIPTION OF THE E3, ITU-T G.832 FRAMES AND ASSOCIATED OVERHEAD BYTES ........................................ 350
Figure 154. Illustration of the E3, ITU-T G.832 Framing Format. ....................................................... 350
6.1.1 Definition of the Overhead Bytes ........................................................................................................... 350
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 351
TABLE 69: DEFINITION OF THE TRAIL TRACE BUFFER BYTES, WITHIN THE E3, ITU-T G.832 FRAMING FORMAT
351
THE MAINTENANCE AND ADAPTATION (MA) BYTE FORMAT ........................................................................ 352
TABLE 70: A LISTING OF THE VARIOUS PAYLOAD TYPE VALUES AND THEIR CORRESPONDING MEANING ... 353
6.2 THE TRANSMIT SECTION OF THE XRT72L58 (E3 MODE OPERATION) .................................................................. 353
Figure 155. A Simple Illustration of the Transmit Section, within the XRT72L58, when it has been configured
to operate in the E3 Mode ................................................................................................................... 354
6.2.1 The Transmit Payload Data Input Interface Block ................................................................................. 354
Figure 156. A Simple Illustration of the Transmit Payload Data Input Interface Block ....................... 355
TABLE 71: LISTING AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE TRANSMIT PAYLOAD DATA INPUT IN-
TERFACE ............................................................................................................................................... 356
Figure 157. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data Input In-
terface block of the XRT72L58 for Mode 1 (Serial/Loop-Timed) Operation ........................................ 358
Figure 158. Behavior of the Terminal Interface signals between the Transmit Payload Data Input Interface
block of the XRT72L58 and the Terminal Equipment (for Mode 1 Operation) .................................... 359
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 359
Figure 159. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data Input In-
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