XRT72L58 Datasheet, PDF (39/486 Pages) Exar Corporation – EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L58
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
PIN DESCRIPTION FOR THE XRT72L58
PIN #
R23
PIN NAME
WR_R/W
R24
ALE_AS
R25
NibbleLnTF
R26
A(11)
T1
RxOutClk[3]/
RxHDLCDat7[3]
T2
TxLineClk[3]
T3
RxNEG[3]
T4
TxFrameRef[3]
T11
VDD
T12
VDD
TYPE
I
I
I
I
O
DESCRIPTION
Write Data Strobe (Intel Mode):
If the microprocessor interface is operating in the Intel Mode, then this active-
low input pin functions as the WR (Write Strobe) input signal from the µP.
Once this active-low signal is asserted, then the Framer will latch the contents
of the µP Data Bus, into the addressed register (or RAM location) within the
Framer. In the Intel Mode, data gets latched on the rising edge of WR
R/W Input Pin (Motorola Mode):
When the Microprocessor Interface Section is operating in the Motorola
Mode, then this pin is functionally equivalent to the R/W pin. In the Motorola
Mode, a READ operation occurs if this pin is at a logic "1". Similarly, a WRITE
operation occurs if this pin is at a logic "0".
Address Latch Enable/Address Strobe:
This input is used to latch the address (present at the Microprocessor Inter-
face Address Bus, A(11:0) into the Framer Microprocessor Interface circuitry
and to indicate the start of a READ/WRITE cycle. This input is active-high in
the Intel Mode (MOTO = "low") and active-low in the Motorola Mode (MOTO =
"high").
Nibble Interface Select Input Pin:
This input pin allows the user to configure the Transmit Payload Data Input
Interface and the Receive Payload Data Output Interface to operate in either
the "Serial-Mode" or the "Nibble/Parallel-Mode".
Setting this input pin "high" configures the Transmit and Receive Terminal
Interfaces to operate in the "Nibble/Parallel-Mode". In this mode, the “Transmit
Payload Data Input Interface” block will accept the “outbound” payload data
(from the Terminal Equipment) in a “nibble-parallel” manner via the
“TxNib[3:0]” input pins. Further, the “Receive Payload Data Output Interface”
block will output the “inbound” payload data (to the Terminal Equipment) in a
“nibble-parallel” manner via the “RxNib[3:0]” output pin.
Setting this input pin "low" configures the Transmit and Receive Terminal
Interfaces to operate in the "Serial" Mode. In this mode, the “Transmit Payload
Data Input Interface” block will accept the “outbound” payload data (from the
Terminal Equipment) in a “serial” manner via the “TxSer” input pin. Further,
the “Receive Payload Data Output Interface” block will output the “inbound”
payload data (to the Terminal Equipment) in a “serial” manner via the “RxSer”
output pin.
Address Bus Input (Microprocessor Interface) - MSB (Most Significant
Bit):
This input pin, along with inputs A0 - A10 are used to select the on-chip
Framer register and RAM space for READ/WRITE operations with the "local"
microprocessor.
See Description of Pin F2
O
See Description of Pin D1
I
See Description of Pin F3
I
See Description of Pin H1
**** Power Supply 3.3V + 5%
**** Power Supply 3.3V + 5%
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