XRT72L58 Datasheet, PDF (82/486 Pages) Exar Corporation – EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L58
REV. P1.1.2
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
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PRELIMINARY
Address Bus into its own circuitry. At this point,
the initial address of the burst access has now
been selected.
A.5 Further, the µC/µP should indicate that this cur-
rent bus cycle is a Write operation by toggling
the WR_R/W (R/W*) input pin "Low".
A.6 The µC/µP should then place the byte or word
that it intends to write into the target register, on
the bi-directional data bus, D[7:0].
A.7 Next, the µC/µP should initiate the bus cycle by
toggling the RD_DS (Data Strobe) input pin
"Low". When the XRT72L58 DS3/E3 Framer
device senses that the WR_R/W input pin is
"Low", and that the RD_DS input pin has tog-
gled "Low" it will enable the input drivers of the
bi-directional data bus, D[7:0].
A.8 After waiting the appropriate amount of time, for
this newly placed data to settle on the bi-direc-
tional data bus (e.g., the Data Setup time) the
Framer will assert the RDY_DTCK (DTACK) out-
put signal.
A.9 After the µP/µC detects the RDY_DTCK signal
(from the Framer) it should toggle the RD_DS
input pin "High". This action accomplishes two
things:
a. It latches the contents of the bi-directional data
bus into the XRT72L58 DS3/E3 Framer Micropro-
cessor Interface block.
b. It terminates the Write cycle.
Figure 35 presents a timing diagram which illustrates
the behavior of the Microprocessor Interface signals,
during the Initial write operation within a Burst Ac-
cess, for a Motorola-type µC/µP.
FIGURE 35. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING THE INITIAL WRITE OPERATION OF
A BURST CYCLE (MOTOROLA-TYPE PROCESSOR)
ALE_AS
A(11:0)
CS
D(7:0)
RD_DS
WR_R/W
RDY_DTCK
Address of "Initial" Target Register (Offset = 0x00)
Data to be Written
(Offset = 0x00)
At the completion of this initial write cycle, the µC/µP
has written a byte or word into the first register or
buffer location (within the XRT72L58 DS3/E3 Framer)
for this particular burst I/O access. In order to illus-
trate how this burst I/O cycle works, the byte (or word)
of data, that is being written in Figure 35 has been la-
beled Data to be Written (Offset = 0x00).
2.3.2.2.2.2.2 The Subsequent Write Operations
The procedure that the µC/µP must use to perform
the remaining write cycles, within this burst access
operation, is presented below.
B.0 Execute each subsequent write cycle, as
described in Steps B.1 through B.3
B.1 Without toggling the ALE_AS (Address Strobe)
input pin (e.g., keeping it "High"), apply the
value of the next byte or word (to be written into
the Framer) to the bi-directional data bus pins,
D[7:0].
B.2 Toggle the RD_DS (Data Strobe) input pin
"Low". This step accomplishes the following.
a. The Framer internally increments the latched
address value (within the Microprocessor Inter-
face).
b. The input drivers of the bi-directional data bus are
enabled.
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