XRT72L58 Datasheet, PDF (270/486 Pages) Exar Corporation – EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L58 EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
Bit 1 (RxLAPD Interrupt Enable) within the RxDS3
LAPD Control Register, as indicated below.
RXDS3 LAPD CONTROL REGISTER (ADDRESS = 0X18)
áç
PRELIMINARY
BIT 7
RO
0
BIT 6
RO
0
BIT 5
Not Used
RO
0
BIT 4
RO
0
BIT 3
RO
0
BIT 2
RxLAPD
Enable
R/W
0
BIT 1
RxLAPD
Interrupt
Enable
R/W
X
BIT 0
RxLAPD
Interrupt
Status
RUR
0
Writing a “1” into this bit-field enables the Receive
LAPD Message Interrupt. Conversely, writing a “0”
into this bit-field disables the Receive LAPD Message
interrupt.
Servicing the Receive LAPD Message Interrupt
Whenever the XRT72L58 Framer IC generates this
interrupt, it will do the following.
• It will assert the Interrupt Request output pin (INT)
by driving it "Low".
• It will set Bit 0 (RxLAPD Interrupt Status), within the
Rx DS3 LAPD Control Register to “1”, as indicated
below.
RXDS3 LAPD CONTROL REGISTER (ADDRESS = 0X18)
BIT 7
RO
0
BIT 6
RO
0
BIT 5
Not Used
RO
0
BIT 4
RO
0
BIT 3
RO
0
BIT 2
RxLAPD
Enable
R/W
0
BIT 1
RxLAPD
Interrupt
Enable
R/W
1
BIT 0
RxLAPD
Interrupt
Status
RUR
1
• It will write the contents of this newly Received
LAPD Message into the Receive LAPD Message
buffer (located at 0xDE through 0x135).
Whenever the Terminal Equipment encounters the
Receive LAPD Interrupt, then it should read out the
contents of the Receive LAPD Message buffer, and
respond accordingly.
251