XRT72L58 Datasheet, PDF (161/486 Pages) Exar Corporation – EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L58
REV. P1.1.2
Figure 39 presents a simple circuit schematic that de-
picts how the XRT72L58 DS3/E3 Framer IC could be
interfaced to the XRT7300 DS3/E3/STS-1 LIU IC.
FIGURE 39. SCHEMATIC DEPICTING HOW TO INTERFACE THE XRT72L58 DS3/E3 FRAMER IC TO THE XRT73L04
DS3/E3/STS-1 LIU IC (ONE CHANNEL SHOWN)
Rx_AIS_Ch_0
RxRED_ALARM_0
Rx_OOF_Ch_0
Rx_LOS_Ch_0
RxFRAME_0
RxSERIAL_CLK_0
RxDATA_IN_0
D[7:0]
A[11:0]
READY_OUT*
ALE
RD*
WR*
XRT72L58_CS*
XRT72L58_INT*
HW_RESET*
TxFRAME_0
44.736MHz
TxDATA_OUT_0
U1
D9
A7
B8
A8
RxAIS_0
RxRED_0
RxOOF_0
RxLOS_0
A9
B9
RxFrame_0
C9 ^RxClk_0
T25
RxSer_0
MOTO
K23
J26
K24
K25
L23
L24
L25
L26
D7
D6
D5
D4
D3
D2
D1
D0
R26
P25
P24
P23
P26
N26
N25
N24
N23
M26
M25
M24
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
J25
R24
U26
R23
T23
J24
Rdy_Dtck
ALE_AS
RD_DS
WR_RW
CS
INT
T24 _RESET
R25 _NIBBLEINTF
B12
H3
C15
TxFrame_0
TxInClk_0
TxSer_0
XRT72L58_Ch_0
RxAVDD_0
DVDD_0
RxPOS_0 ^H2
RxNEG_0 ^G1
RxLineClk_0 ^J4
C5
0.01uF
C4
0.01uF
R7
4.7k
78 _RxAVDD0
58 _RxDVDD0
75
52
LOSTHR_0
HOST/HW
61 _RPOS0
60 _RNEG0/LCV0
59 _RCLK0
U2
TxAVDD0 ⁴⁷
TxAVDD0 ³³
RTIP0 ⁸⁰
RRING0 ⁷⁹
ExtLOS_0 ^J3
LIU_RLOL_0
LIU_CS*
LIU_SCLK
LIU_SDI
LIU_SDO
LIU_RESET*
NOTE: LIU Microprocessor
Interface signals originate
from external glue logic _{X M T R _ O F F}
TxPOS_0 ^J1
TxNEG_0 ^K4
TxLineClk_0 ^J2
65
64
RLOL_0
RLOS_0
69
70
71
72
110
CS
SCLK
SDI
SDO
REG_RESET*
131 _TxOFF
41 _{TPDATA_0}
40 _{TNDATA_0}
42
66
TCLK_0
EXCLK_0
TTIP0 ³⁴
TRING0 ³²
MTIP0 ³⁵
54 _RxDGND0
73
RxAGND0
MRING0 ³⁶
TxAGND0 ³¹
49
TxAGND0
XRT73L04IV_Ch_0
C2
0.01uF
C3
0.01uF
TxAVDD_0
R1
R2
37.4
37.4
C1
0.01uF
6 _T2 1
43
T3001
R3
31.6
1 _T1 6
R4
34
T3001
R5
31.6
270
R6
270
J1
BNC
1
J2
BNC
1
3.1 BIT-FIELDS WITHIN THE LINE INTERFACE DRIVE
REGISTER
As mentioned above, the Line Interface Drive and
Scan section consists of five output pins and three in-
put pins. The logic state of the output pins are con-
trolled by the contents within the Line Interface Drive
register, as depicted below.
LINE INTERFACE DRIVE REGISTER (ADDRESS = 0X80)
BIT 7
ILOOP
BIT 6
BIT 5
REQB
BIT 4
TAOS
BIT 3
ENCODIS
BIT 2
TXLEV
BIT 1
RLOOP
BIT 0
LLOOP
R/O
R/O
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
1
0
0
0
The role of each of these bit-fields are their corre-
sponding output pins are depicted below.
Bit 7 - ILOOP (Internal Remote Loop-back)
This “Read/Write” bit-field permits the user to config-
ure the corresponding channel (within the XRT72L58
device) to operate in the “Internal Remote Loop-back”
Mode. Once the user configures the channel to oper-
142