XRT72L58 Datasheet, PDF (66/486 Pages) Exar Corporation – EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L58
REV. P1.1.2
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
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PRELIMINARY
2.0 THE MICROPROCESSOR INTERFACE
BLOCK
The Microprocessor Interface section supports com-
munication between the local microprocessor (µP)
and the Framer IC. In particular, the Microprocessor
Interface section supports the following operations
between the local microprocessor and the Framer.
• Channel Selection
• The writing of configuration data into the Framer
on-chip (addressable) registers.
• The writing of an outbound PMDL (Path Mainte-
nance Data Link) message into the Transmit LAPD
Message buffer (within the Framer IC).
• The Framer IC's generation of an Interrupt Request
to the µP.
• The µP's servicing of the interrupt request from the
Framer IC.
• The monitoring of the system's health by periodi-
cally reading the on-chip Performance Monitor reg-
isters.
• The reading of an inbound PMDL Message from
the Receive LAPD Message Buffer (within the
Framer IC).
Each of these operations (between the local micro-
processor and the Framer IC) will be discussed in
some detail, throughout this data sheet.
2.1 CHANNEL SELECTION WITHIN THE XRT72L58
DEVICE
The XRT72L58 8-Channel DS3/E3 Clear Channel
Framer IC consists of eight independent banks of
"Configuration" registers. Each of these banks are
identical and correspond to each of the eight chan-
nels within the XRT72L58. The XRT72L58 permits
the user to select and access any one of these Con-
figuration Register Banks, via the three (3) Most Sig-
nificant Address Pins, A9, A10 and A11.
The relationship between the states of A9, A10 and
A11 and the corresponding "Configuration Register"
bank, is tabulated below.
TABLE 1: THE RELATIONSHIP BETWEEN ADDRESS BITS
A9, A10 AND A11 THE SELECTED CONFIGURATION
REGISTER BANK
A11 A10 A9
CONFIGURATION REGISTER BANK
SELECTED
0 0 0 Channel 0
0 0 1 Channel 1
0 1 0 Channel 2
0 1 1 Channel 3
1 0 0 Channel 4
1 0 1 Channel 5
1 1 0 Channel 6
1 1 1 Channel 7
The remaining Address Bus pins [A8 through A0] are
used to select the individual configuration registers
(within the selected configuration register bank) for
Read/Write access.
Looking at this Another Way
Each of the eight (8) Configuration Register Banks,
within the XRT72L58 DS3/E3 Framer IC has an iden-
tical set of configuration registers. However, address
pins A9, A10 and A11 impose the following address
location offset, for each of the Configuration Register
Bank within the address space of the XRT72L58 de-
vice.
CONFIGURATION REGISTER ADDRESS OFFSET (WITHIN THE
BANK - CHANNEL NUMBER XRT72L58 ADDRESS SPACE)
0
0x000
1
0x200
2
0x400
3
0x600
4
0x800
5
0xA00
6
0xC00
7
0xE00
Figure 24 presents a simple block diagram of the Mi-
croprocessor Interface Section, within the Framer IC.
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