XRT72L58 Datasheet, PDF (212/486 Pages) Exar Corporation – EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L58
REV. P1.1.2
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
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PRELIMINARY
The XRT72L58 Framer IC is a digital device that
takes DS3 payload and overhead bit information from
some terminal equipment, processes this data and ul-
timately, multiplexes this information into a series of
outbound DS3 frames. However, for DS3 coaxial ca-
ble applications, the XRT72L58 Framer IC lacks the
current drive capability to be able to directly transmit
this DS3 data stream through some transformer-cou-
pled coax cable with enough signal strength for it to
comply with the Isolated Pulse Template require-
ments and be received by the remote receiver.
Therefore, in order to get around this problem, the
Framer IC requires the use of an LIU (Line Interface
Unit) IC. An LIU is a device that has sufficient drive
capability, along with the necessary pulse-shaping
circuitry to be able to transmit a signal through the
transmission medium in a manner that it can (1) com-
ply with the DSX-3 Isolated Pulse Template require-
ments and (2) be reliably received by the Remote Ter-
minal Equipment. Figure 65 presents a circuit draw-
ing depicting the Framer IC interfacing to an LIU
(XRT7300 DS3/E3/STS-1 Transmit LIU).
FIGURE 65. APPROACH TO INTERFACING THE XRT72L58 FRAMER IC TO THE XRT73L04 DS3/E3/STS-1 TRANS-
MITTER LIU (ONE CHANNEL SHOWN)
Rx_AIS_Ch_0
RxRED_ALARM_0
Rx_OOF_Ch_0
Rx_LOS_Ch_0
RxFRAME_0
RxSERIAL_CLK_0
RxDATA_IN_0
D[7:0]
A[11:0]
READY_OUT*
ALE
RD*
WR*
XRT72L58_CS*
XRT72L58_INT*
HW_RESET*
TxFRAME_0
44.736MHz
TxDATA_OUT_0
U1
D9
A7
B8
A8
RxAIS_0
RxRED_0
RxOOF_0
RxLOS_0
A9
B9
C9
T25
RxFrame_0
RxClk_0
RxSer_0
MOTO
K23
J26
K24
K25
L23
L24
L25
L26
D7
D6
D5
D4
D3
D2
D1
D0
R26
P25
P24
P23
P26
N26
N25
N24
N23
M26
M25
M24
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
J25
R24
U26
R23
T23
J24
Rdy_Dtck
ALE_AS
RD_DS
WR_RW
CS
INT
T24 _RESET
R25 _NIBBLEINTF
B12
H3
C15
TxFrame_0
TxInClk_0
TxSer_0
XRT72L58_Ch_0
RxAVDD_0
DVDD_0
RxPOS_0 ^H2
RxNEG_0 ^G1
RxLineClk_0 ^J4
C5
0.01uF
C4
0.01uF
R7
4.7k
78 _RxAVDD0
58 _RxDVDD0
75
52
LOSTHR_0
HOST/HW
61 _RPOS0
60 _RNEG0/LCV0
59 _RCLK0
U2
TxAVDD0 ⁴⁷
TxAVDD0 ³³
RTIP0 ⁸⁰
RRING0 ⁷⁹
ExtLOS_0 ^J3
LIU_RLOL_0
LIU_CS*
LIU_SCLK
LIU_SDI
LIU_SDO
LIU_RESET*
NOTE: LIU Microprocessor
Interface signals originate
from external glue logic _{XMTR_OFF}
TxPOS_0 ^J1
TxNEG_0 ^K4
TxLineClk_0 ^J2
65
64
RLOL_0
RLOS_0
69
70
71
72
110
CS
SCLK
SDI
SDO
REG_RESET*
131 _TxOFF
41 _{TPDATA_0}
40 _{TNDATA_0}
42
66
TCLK_0
EXCLK_0
TTIP0 ³⁴
TRING0 ³²
MTIP0 ³⁵
54 _RxDGND0
73 _RxAGND0
MRING0 ³⁶
TxAGND0 ³¹
TxAGND0 ⁴⁹
XRT73L04IV_Ch_0
C2
0.01uF
TxAVDD_0
C3
0.01uF
R1
R2
37.4
37.4
C1
0.01uF
6 _T2 1
43
T3001
R3
1 _T1 6
31.6
R4
34
T3001
R5
31.6
270
R6
270
J1
BNC
1
J2
BNC
1
The Transmit Section of the XRT72L58 contains a
block which is known as the Transmit DS3 LIU Inter-
face block. The purpose of the Transmit DS3 LIU In-
terface block is to take the outbound DS3 data
stream, from the Transmit DS3 Framer block, and to
do the following:
1. Encode this data into one of the following line
codes
a. Unipolar (e.g., Single-Rail)
b. AMI (Alternate Mark Inversion)
c. B3ZS (Bipolar 3 Zero Substitution)
2. And to transmit this data to the LIU IC.
Figure 66 presents a simple illustration of the Trans-
mit DS3 LIU Interface block.
193