XRT72L58 Datasheet, PDF (174/486 Pages) Exar Corporation – EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L58
REV. P1.1.2
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
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PRELIMINARY
Figure 44 presents an illustration of the Transmit Pay- being interfaced to the Terminal Equipment, for Mode
load Data Input Interface block (within the XRT72L58) 1 operation.
FIGURE 44. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA
INPUT INTERFACE BLOCK (OF THE XRT72L58) FOR MODE 1(SERIAL/LOOP-TIMING) OPERATION
DS3_Clock_In
DS3_Data_Out
Tx_Start_of_Frame
DS3_Overhead_Ind
44.736 MHz
RxOutClk
TxSer
TxFrame
TxOH_Ind
NibInt
Terminal Equipment
XRT72L5x DS3 Framer
Mode 1, Operation of the Terminal Equipment
When the XRT72L58 is operating in this mode, it will
function as the source of the 44.736MHz clock signal
(via the RxOutClk signal). This clock signal will be
used as the Terminal Equipment Interface clock by
both the XRT72L58 IC and the Terminal Equipment.
The Terminal Equipment will serially output the pay-
load data of the outbound DS3 data stream via its
DS3_Data_Out pin. The Terminal Equipment will up-
date the data on the DS3_Data_Out pin upon the ris-
ing edge of the 44.736 MHz clock signal, at its
DS3_Clock_In input pin (as depicted in Figure 44 and
Figure 45).
The XRT72L58 will latch the outbound DS3 data
stream (from the Terminal Equipment) on the rising
edge of the RxOutClk signal.
The XRT72L58 will indicate that it is processing the
last bit, within a given outbound DS3 frame, by puls-
ing its TxFrame output pin "High" for one bit-period.
When the Terminal Equipment detects this pulse at its
Tx_Start_of_Frame input, it is expected to begin
transmission of the very next outbound DS3 frame to
the XRT72L58 via the DS3_Data_Out (or TxSer pin).
Finally, the XRT72L58 will indicate that it is about to
process an overhead bit by pulsing the TxOH_Ind
output pin "High" one bit period prior to its processing
of an OH (Overhead) bit. In Figure 44, the TxOH_Ind
output pin is connected to the DS3_Overhead_Ind in-
put pin of the Terminal Equipment. Whenever the
DS3_Overhead_Ind pin is pulsed "High" the Terminal
Equipment is expected to not transmit a DS3 payload
bit upon the very next clock edge. Instead, the Termi-
nal Equipment is expected to delay its transmission of
the very next payload bit, by one clock cycle.
The behavior of the signals, between the XRT72L58
and the Terminal Equipment, for DS3 Mode 1 opera-
tion is illustrated in Figure 45.
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