XRT72L58 Datasheet, PDF (222/486 Pages) Exar Corporation – EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L58
REV. P1.1.2
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
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PRELIMINARY
II/O CONTROL REGISTER (ADDRESS = 0X01)
BIT 7
BIT 6
BIT 5
BIT 4
Disable TxLOC
R/W
1
LOC
RO
0
Disable
RxLOC
R/W
1
AMI/ZeroSup*
R/W
0
Table 36 relates the value of this bit-field to the Re-
ceive DS3 LIU Interface Input Mode.
BIT 3
Unipolar/
Bipolar*
R/W
0
BIT2
TxLine CLK
Invert
R/W
0
BIT 1
RxLine CLK
Invert
R/W
0
BIT 0
Reframe
R/W
0
TABLE 36: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON
BIT 3
0
1
RECEIVE DS3 LIU INTERFACE INPUT MODE
.Bipolar Mode (Dual Rail): AMI or B3ZS Line Codes are Transmitted and Received.
Unipolar Mode (Single Rail) Mode of transmission and reception of DS3 data is selected.
NOTES:
1. The default condition is the Bipolar Mode.
2. This selection also effects the Transmit DS3 Framer
Line Interface Output Mode
4.3.1.2 Bipolar Decoding
If the Receive DS3 LIU Interface block is operating in
the Bipolar Mode, then it will receive the DS3 data
pulses via both the RxPOS, RxNEG, and the RxLi-
neClk input pins. Figure 75 presents a circuit dia-
gram illustrating how the Receive DS3 LIU Interface
block interfaces to the Line Interface Unit while the
Framer is operating in Bipolar mode. The Receive
DS3 LIU Interface block can be configured to decode
the incoming data from either the AMI or B3ZS line
codes.
FIGURE 75. ILLUSTRATION ON HOW THE RECEIVE DS3 FRAMER (WITHIN THE XRT72L58 FRAMER IC) BEING INTER-
FACED TO THEXRT73L04 LIU, WHILE THE FRAMER IS OPERATING IN BIPOLAR MODE (ONE CHANNEL SHOWN)
Rx_AIS_Ch_0
RxRED_ALARM_0
Rx_OOF_Ch_0
Rx_LOS_Ch_0
RxFRAME_0
RxSERIAL_CLK_0
RxDATA_IN_0
D[7:0]
A[11:0]
READY_OUT*
ALE
RD*
WR*
XRT72L58_CS*
XRT72L58_INT*
HW_RESET*
TxFRAME_0
44.736MHz
TxDATA_OUT_0
U1
D9
A7
B8
A8
RxAIS_0
RxRED_0
RxOOF_0
RxLOS_0
A9
B9
C9
T25
RxFrame_0
RxClk_0
RxSer_0
MOTO
K23
J26
D7
K24
K25
L23
L24
L25
D6
D5
D4
D3
D2
L26
D1
D0
R26
P25
P24
P23
P26
N26
N25
A11
A10
A9
A8
A7
A6
N24
N23
M26
M25
M24
A5
A4
A3
A2
A1
A0
J25
R24
U26
Rdy_Dtck
ALE_AS
R23
T23
J24
RD_DS
WR_RW
CS
INT
T24 _RESET
R25 _NIBBLEINTF
B12
H3
C15
TxFrame_0
TxInClk_0
TxSer_0
XRT72L58_Ch_0
RxAVDD_0
DVDD_0
RxPOS_0 ^H2
RxNEG_0 ^G1
RxLineClk_0 ^J4
C5
0.01uF
C4
0.01uF
R7
4.7k
78 _RxAVDD0
58
RxDVDD0
75
52
LOSTHR_0
HOST/HW
61 _RPOS0
60 _RNEG0/LCV0
59 _RCLK0
U2
TxAVDD0 ⁴⁷
33
TxAVDD0
RTIP0 ⁸⁰
RRING0 ⁷⁹
ExtLOS_0 ^J3
LIU_RLOL_0
LIU_CS*
LIU_SCLK
LIU_SDI
LIU_SDO
LIU_RESET*
NOTE: LIU Microprocessor
Interface signals originate
from external glue logic _{XMTR_OFF}
TxPOS_0 ^J1
TxNEG_0 ^K4
TxLineClk_0 ^J2
65
64
RLOL_0
RLOS_0
69
70
71
72
110
CS
SCLK
SDI
SDO
REG_RESET*
131 _TxOFF
41 _{TPDATA_0}
40 _{TNDATA_0}
42
66
TCLK_0
EXCLK_0
TTIP0 ³⁴
TRING0 ³²
MTIP0 ³⁵
54
RxDGND0
73 _RxAGND0
MRING0 ³⁶
31
TxAGND0
TxAGND0 ⁴⁹
XRT73L04IV_Ch_0
C2
0.01uF
TxAVDD_0
C3
0.01uF
R1
R2
37.4
37.4
C1
0.01uF
6 _T2 1
43
T3001
R3
1 _T1 6
31.6
R4
34
T3001
R5
31.6
270
R6
270
J1
BNC
1
J2
BNC
1
203