XRT72L58 Datasheet, PDF (69/486 Pages) Exar Corporation – EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L58
REV. P1.1.2
TABLE 4: PIN DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS WHILE THE MICROPROCESSOR
INTERFACE IS OPERATING IN THE MOTOROLA MODE
PIN NAME
EQUIVALENT PIN
IN MOTOROLA
ENVIRONMENT
TYPE
DESCRIPTION
ALE_AS
AS*
I Address Strobe: This "active-low" signal is used to latch the contents on the
address bus input pins: A[11:0] into the Microprocessor Interface circuitry. The
contents of the Address Bus are latched into the UNI device on the rising edge of
the ALE_AS signal. This signal can also be used to indicate the start of a burst
cycle.
RD_DS
DS*
I Data Strobe: This signal latches the contents of the bi-directional data bus pins
into the Addressed Register (within the UNI) during a Write Cycle.
WR_R/W
R/W*
I Read/Write* Input: When this pin is "High", it indicates a Read Cycle. When this
pin is "Low", it indicates a Write cycle.
RDY_DTCK
DTACK*
O Data Transfer Acknowledge: The UNI device asserts DTACK* in order to inform
the CPU that the present READ or WRITE cycle is nearly complete. The 68000
family of CPUs requires this signal from its peripheral devices, in order to quickly
and properly complete a READ or WRITE cycle.
2.3 INTERFACING THE XRT72L58 DS3/E3 FRAMER
TO THE LOCAL µC/µP VIA THE MICROPROCESSOR
INTERFACE BLOCK
The Microprocessor Interface block, within the Fram-
er device is very flexible and provides the following
options to the user.
• To interface the Framer device to a µC/µP over an
8-bit wide bi-directional data bus.
• To interface the Framer to an Intel-type or Motorola-
type µC/µP.
• To transfer data (between the Framer IC and the
µC/µP) via the Programmed I/O or Burst Mode
Each of the options are discussed in detail below.
Section 2.3.1 will discussed the issues associated
with interfacing the Framer to a µC/µP over an 8-bit
bi-directional data bus. Afterwards, Section 2.3.2 will
discuss Data Access (e.g., Programmed I/O and
Burst) Mode when interfaced to both Motorola-type
and Intel-type µC/µP.
2.3.1 Interfacing the XRT72L58 DS3/E3 Framer
to the Microprocessor over an 8 bit wide bi-direc-
tional Data Bus
The XRT72L58 DS3/E3 Framer Microprocessor Inter-
face permits the user to interface it to a µC/µP over an
8-bit wide bi-directional data bus.
2.3.1.1 Interfacing the Framer to the µC/µP
over an 8-bit wide bi-directional data bus.
In general, interfacing the Framer to an 8-bit µC/µP is
quite straight-forward. This is because most of the
registers, within the Framer, are 8-bits wide. Further,
in this mode, the µC/µP can read or write data into
both even and odd numbered addresses within the
Framer address space.
Reading Performance Monitor (PMON) Registers
The only awkward issue that the user should be wary
of (while operating in the 8-bit mode) occurs whenev-
er the µC/µP needs to read the contents of one of the
PMON (Performance Monitor) registers.
The XRT72L58 DS3/E3 Framer Device consists of
the following PMON Registers.
• PMON LCV Event Count Register
• PMON Framing Error Event Count Register
• PMON Received FEBE Event Count Register
• PMON Parity Error Event Count Register
• PMON Received Single-Bit HEC Error Count Reg-
ister
• PMON Received Multiple-Bit HEC Error Count
Register
• PMON Received Idle Cell Count Register
• PMON Received Valid Cell Count Register
• PMON Discarded Cell Count Register
• PMON Transmitted Idle Cell Count Register
• PMON Transmitted Valid Cell Count Register.
Unlike most of the registers within the Framer, the
PMON registers are 16-bit registers (or 16-bits wide).
Table 5 lists each of these PMON registers as con-
sisting of two 8-bit registers. One of these 8-bit regis-
ter is labeled MSB (or Most Significant Byte) and the
other register is labeled LSB (or Least Significant
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