XRT72L58 Datasheet, PDF (31/486 Pages) Exar Corporation – EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L58
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
PIN DESCRIPTION FOR THE XRT72L58
PIN #
D1
PIN NAME
TxLineClk[7]
D2
TRST
D3
RxNib2[7]/
RxHDLCDat2[7]
D4
TxAISEn[7]
D5
RxClk[7]
D6
RxOHInd[7]
D7
TxOH[7]/
TxHDLCDat5[7]
D8
TxOHIns[7]/
TxHDLCDat4[7]
D9
RxLOS[7]
D10
TxOHClk[7]
D11
RxNib3[0]/
RxHDLCDat3[0]
D12
RxNib1[0]/
RxHDLCDat1[0]
D13
TxNibClk[0]/
SndFCS[0]
D14
TxNib1[0]/
TxHDLCDat1[0]
D15
TxNib2[0]/
TxHDLCDat2[0]
D16
RxOOF[5]
D17
RxFrame[5]
D18
RxSer[5]/
RxIdle[5]
D19
TxFrame[5]
D20
TxOHFrame[5]/
TxHDLCClk[5]
D21
TxNib1[5]/
TxHDLCDat1[5]
TYPE
O
I
O
DESCRIPTION
Transmit Line Interface Clock:
This clock signal is output to the Line Interface Framer, along with the TxPOS
and TxNEG signals. The purpose of this output clock signal is to provide the
LIU with timing information that it can use to generate the AMI pulses and
deliver them over the transmission medium to the Far-End Receiver. The user
can configure the source of this clock to be either the RxLineClk (from the
Receiver portion of the Framer) or the TxInClk input. The nominal frequency
of this clock signal is 34.368 MHz.
JTAG Reset Pin: Resets Boundary Scan Logic
See Description of Pin A10
I
See Description of Pin A22
O
See Description of Pin B9
O
See Description of Pin C11
I
See Description of Pin A15
I
See Description of Pin A16
O
See Description of Pin A8
O
See Description of Pin A13
O
See Description of Pin A19
O
See Description of Pin A5
O
See Description of Pin A2
I
I
See Description of Pin B5
I
See Description of Pin B6
O
See Description of Pin B8
O
See Description of Pin A9
O
See Description of Pin B25
O
See Description of Pin B2
O
See Description of Pin A4
I
See Description of Pin B5
12