XRT72L58 Datasheet, PDF (285/486 Pages) Exar Corporation – EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L58
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
0
0
1
0
3. Interface the XRT72L58, to the Terminal Equip-
ment, as illustrated in Figure 106.
NOTE: The XRT72L58 Framer IC cannot support the
Framer Local Loop-back Mode of operation, while operating
in Mode 4. The user must configure the XRT72L58 Framer
IC into any of the following modes prior to configuring the
Framer Local Loop-back Mode operation.
• Mode 2 - Serial/Local-Timed/Frame-Slave Mode
• Mode 3 - Serial/Local-Timed/Frame-Master Mode
• Mode 5 - Nibble-Parallel/Local-Timed/Frame-Slave
Mode
• Mode 6 - Nibble-Parallel/Local-Timed/Frame-Mas-
ter Mode.
For more detailed information on the Framer Local
Loop-back Mode, please see Section 6.0.
5.2.1.5 Mode 5 - The Nibble-Parallel/Local-
Timed/Frame-Slave Interface Mode Behavior of
the XRT72L58
If the XRT72L58 has been configured to operate in
this mode, then the XRT72L58 will function as fol-
lows:
A. Local-Timed - Uses the TxInClk signal as the
Timing Reference
In this mode, the Transmit Section of the XRT72L58
will use the TxInClk signal at its timing reference.
Further, the chip will internally divide the TxInClk
clock signal by a factor of 4 and will output this divid-
ed clock signal via the TxNibClk output pin. The
Transmit Terminal Equipment Input Interface block
(within the XRT72L58) will use the rising edge of the
BIT 3
BIT2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
0
0
0
TxNibClk signal, to latch the data, residing on the Tx-
Nib[3:0] into its circuitry.
B. Nibble-Parallel Mode
The XRT72L58 will accept the E3 payload data, from
the Terminal Equipment, in a parallel manner, via the
TxNib[3:0] input pins. The Transmit Terminal Equip-
ment Input Interface will latch this data into its circuit-
ry, on the rising edge of the TxNibClk output signal.
C. Delineation of outbound E3 Frames
The Transmit Section will use the TxInClk input signal
as its timing reference and will use the TxFrameRef
input signal as its Framing Reference (e.g., the Trans-
mit Section of the XRT72L58 initiates frame genera-
tion upon the rising edge of the TxFrameRef signal).
D. Sampling of payload data, from the Terminal
Equipment
In Mode 5, the XRT72L58 will sample the data, at the
TxNib[3:0] input pins, on the third rising edge of the
TxInClk clock signal, following a pulse in the TxNibClk
signal (see Figure 108).
NOTE: The TxNibClk signal, from the XRT72L58 operates
nominally at 8.592 MHz (e.g., 34.368 MHz divided by 4).
Interfacing the Transmit Payload Data Input Inter-
face block of the XRT72L58 to the Terminal Equip-
ment for Mode 5 Operation
Figure 108 presents an illustration of the Transmit
Payload Data Input Interface block (within the
XRT72L58) being interfaced to the Terminal Equip-
ment, for Mode 5 Operation.
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