XRT72L58 Datasheet, PDF (28/486 Pages) Exar Corporation – EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L58
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
áç
PRELIMINARY
PIN DESCRIPTION FOR THE XRT72L58
PIN #
B9
PIN NAME
RxClk[0]
B10
RxOHClk[0]/
RxHDLCClk[0]
B11
RxOH[0]/
RxHDLCDat6[0]
B12
TxFrame[0]
B13
TxOHFrame[0]/
TxHDLCClk[0]
B14
TxAISEn[0]
B15
TxNib3[0]/
TxHDLCDat3[0]
B16
RxLOS[5]
B17
RxOHClk[5]/
RxHDLCClk[5]
B18
RxNib1[5]/
RxHDLCDat1[5]
B19
RxClk[5]
B20
TxNibClk[5]/
SndFCS[5]
B21
TxOHClk[5]
TYPE
O
O
DESCRIPTION
Receive Clock Output Signal for Serial and Nibble/Parallel Data Inter-
face:
The exact behavior of this signal depends upon whether the XRT72L58 is
operating in the "Serial" or in the "Nibble-Parallel-Mode".
Serial Mode Operation:
In the "serial" mode, this signal is a 44.736MHz clock output signal (for DS3
applications) or 34.368MHz clock output signal (for E3 applications). The
Receive Payload Data Output Interface will update the data via the RxSer out-
put pin, upon the rising edge of this clock signal.
The user is advised to design (or configure) the Terminal Equipment to sam-
ple the data on the "RxSer" pin, upon the falling edge of this clock signal.
Nibble-Parallel Mode Operation:
In this Nibble-Parallel Mode, the XRT72L58 will derive this clock signal, from
the RxLineClk signal. The XRT72L58 will pulse this clock signal 1176 times
for each "inbound" DS3 frame (or 1074 times for each inbound “E3/ITU-T
G.832” frame, or 384 times for each inbound “E3/ITU-T G.751 frame). The
Receive Payload Data Output Interface will update the data, on the
"RxNib[3:0]" output pins upon the falling edge of this clock signal.
NOTE: The user is advised to design (or configure) the Terminal Equipment to
sample the data on the "RxNib[3:0] output pins, upon the rising edge of this
clock signal
See Description of Pin A7
O
Receive Overhead Output Port:
All overhead bits, which are received via the "Receive Section" of the Framer;
will be output via this output pin, upon the rising edge of RxOHClk.
Recieve HDLC Data Output - 6:
This pin contains bit 6 RxHDLC data when the HDLC controller is turned on.
O
See Description of Pin B2
O
See Description of Pin A4
I
See Description of Pin A22
I
See Description of Pin A1
O
See Description of Pin A8
O
See Description of Pin A7
O
See Description of Pin A5
O
See Description of Pin B9
O
See Description of Pin A2
I
O
See Description of Pin A13
9