XRT83L30 Datasheet, PDF (8/78 Pages) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L30
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SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.3.0
PRELIMINARY
SIGNAL NAME
RNEG
LCV
RPOS
RDATA
RTIP
RRING
RXMUTE
RCLKE
PIN #
1
2
4
5
50
53
TYPE
O
DESCRIPTION
Receiver Negative Data Output
In dual-rail mode, this signal is the receiver negative-rail output data.
Line Code Violation Output
In single-rail mode, this signal goes ‘High’ for one RCLK cycle to indicate a
code violation is detected in the received data. If AMI coding is selected,
every bipolar violation received will cause this pin to go “High”.
O Receiver Positive Data Output
In dual-rail mode, this signal is the receive positive-rail output data sent to the
Framer.
Receiver NRZ Data Output
In single-rail mode, this signal is the receive NRZ format output data sent to
the Framer.
I
Receiver Differential Tip Positive Input
Positive differential receive input from the line.
I
Receiver Differential Ring Negative Input
Negative differential receive input from the line.
I
Receive Muting
In Hardware mode, connect this pin ‘High’ to mute RPOS and RNEG outputs
to a “Low” state upon receipt of LOS condition to prevent data chattering.
Connect this pin to ‘Low’ to disable muting function.
NOTE: Internally pulled "Low" with 50kΩ resistor.
I
Receive Clock Edge
In Hardware mode, with this pin set to ‘High’ the output receive data is
updated on the falling edge of RCLK. With this pin tied ‘Low’, output data is
updated on the rising edge of RCLK.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
5