XRT83L30 Datasheet, PDF (4/78 Pages) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L30
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SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.3.0
PRELIMINARY
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
APPLICATIONS .............................................................................................................................................. 1
FEATURES .................................................................................................................................................... 1
Figure 1. Block Diagram of the XRT83L30 T1/E1/J1 LIU (Host Mode) ................................................. 1
Figure 2. Block Diagram of the XRT83L30 T1/E1/J1 LIU (Hardware Mode) ......................................... 2
FEATURES .................................................................................................................................................... 2
ORDERING INFORMATION ............................................................................................................... 3
Figure 3. Pin Out of the XRT83L30 .......................................................................................................... 3
TABLE OF CONTENTS ....................................................................................................... I
PIN DESCRIPTIONS BY FUNCTION ................................................................................. 4
SERIAL INTERFACE ....................................................................................................................................... 4
RECEIVER .................................................................................................................................................... 4
TRANSMITTER ............................................................................................................................................... 6
JITTER ATTENUATOR .................................................................................................................................... 8
CLOCK SYNTHESIZER .................................................................................................................................... 9
REDUNDANCY SUPPORT .............................................................................................................................. 11
TERMINATIONS ........................................................................................................................................... 11
CONTROL FUNCTION ................................................................................................................................... 13
ALARM FUNCTION/OTHER ........................................................................................................................... 14
POWER AND GROUND ................................................................................................................................. 16
FUNCTIONAL DESCRIPTION ......................................................................................... 17
MASTER CLOCK GENERATOR ...................................................................................................................... 17
Figure 4. Two Input Clock Source ......................................................................................................... 17
Figure 5. One Input Clock Source ......................................................................................................... 17
RECEIVER ........................................................................................................................ 18
RECEIVER INPUT ......................................................................................................................................... 18
TABLE 1: MASTER CLOCK GENERATOR ...................................................................................................... 18
RECEIVE MONITOR MODE ........................................................................................................................... 19
RECEIVER LOSS OF SIGNAL (RLOS) ........................................................................................................... 19
Figure 6. Simplified Diagram of -15dB T1/E1 Short Haul Mode and RLOS Condition ..................... 19
Figure 7. Simplified Diagram of -29dB T1/E1 Gain Mode and RLOS Condition ............................... 20
Figure 8. Simplified Diagram of -36dB T1/E1 Long Haul Mode and RLOS Condition ...................... 20
RECEIVE HDB3/B8ZS DECODER ................................................................................................................ 21
RECOVERED CLOCK (RCLK) SAMPLING EDGE ............................................................................................ 21
Figure 9. Simplified Diagram of Extended RLOS mode (E1 Only) ..................................................... 21
Figure 10. Receive Clock and Output Data Timing ............................................................................. 21
JITTER ATTENUATOR .................................................................................................................................. 22
GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH) ................................................................. 22
TABLE 2: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS ............................................... 22
ARBITRARY PULSE GENERATOR .................................................................................................................. 23
TRANSMITTER ................................................................................................................. 23
DIGITAL DATA FORMAT ............................................................................................................................... 23
TRANSMIT CLOCK (TCLK) SAMPLING EDGE ................................................................................................ 23
Figure 11. Arbitrary Pulse Segment Assignment ................................................................................ 23
TRANSMIT HDB3/B8ZS ENCODER .............................................................................................................. 24
Figure 12. Transmit Clock and Input Data Timing ............................................................................... 24
TABLE 3: EXAMPLES OF HDB3 ENCODING ................................................................................................. 24
TABLE 4: EXAMPLES OF B8ZS ENCODING .................................................................................................. 24
DRIVER FAILURE MONITOR (DMO) .............................................................................................................. 25
TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT ...................................................................... 25
TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS .................................. 25
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