XRT83L30 Datasheet, PDF (5/78 Pages) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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XRT83L30
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.0
TRANSMIT AND RECEIVE TERMINATIONS .................................................................. 27
RECEIVER ............................................................................................................................................... 27
Internal Receive Termination Mode ................................................................................................................. 27
TABLE 6: RECEIVE TERMINATION CONTROL ................................................................................................ 27
Figure 13. Simplified Diagram for the Internal Receive and Transmit Termination Mode .............. 27
TABLE 7: RECEIVE TERMINATIONS ............................................................................................................. 28
Figure 14. Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0) ................... 28
TRANSMITTER ........................................................................................................................................ 29
Transmit Termination Mode ............................................................................................................................. 29
External Transmit Termination Mode ............................................................................................................... 29
Figure 15. Simplified Diagram for E1 in External Termination Mode (RXTSEL= 0) ......................... 29
TABLE 8: TRANSMIT TERMINATION CONTROL ............................................................................................. 29
TABLE 9: TERMINATION SELECT CONTROL ................................................................................................. 29
REDUNDANCY APPLICATIONS ............................................................................................................. 30
TABLE 10: TRANSMIT TERMINATION CONTROL ........................................................................................... 30
TABLE 11: TRANSMIT TERMINATIONS ......................................................................................................... 30
TYPICAL REDUNDANCY SCHEMES ..................................................................................................... 31
Figure 16. Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy ............. 32
Figure 17. Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy .................... 32
Figure 18. Simplified Block Diagram - Transmit Section for N+1 Redundancy ............................... 33
Figure 19. Simplified Block Diagram - Receive Section for N+1 Redundancy ................................. 34
PATTERN TRANSMIT AND DETECT FUNCTION ............................................................................................... 35
TRANSMIT ALL ONES (TAOS) .................................................................................................................... 35
NETWORK LOOP CODE DETECTION AND TRANSMISSION .............................................................................. 35
TABLE 12: PATTERN TRANSMISSION CONTROL ............................................................................................ 35
TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS) ......................................................... 36
TABLE 13: LOOP-CODE DETECTION CONTROL ........................................................................................... 36
LOOP-BACK MODES ................................................................................................................................... 38
LOCAL ANALOG LOOP-BACK (ALOOP) ....................................................................................................... 38
TABLE 14: LOOP-BACK CONTROL IN HARDWARE MODE .............................................................................. 38
TABLE 15: LOOP-BACK CONTROL IN HOST MODE ........................................................................................ 38
Figure 20. Local Analog Loop-back signal flow .................................................................................. 38
REMOTE LOOP-BACK (RLOOP) ................................................................................................................. 39
Figure 21. Remote Loop-back mode with jitter attenuator selected in receive path ....................... 39
Figure 22. Remote Loop-back mode with jitter attenuator selected in Transmit path .................... 39
DIGITAL LOOP-BACK (DLOOP) .................................................................................................................. 40
DUAL LOOP-BACK ...................................................................................................................................... 40
Figure 23. Digital Loop-back mode with jitter attenuator selected in Transmit path ...................... 40
Figure 24. Signal flow in Dual loop-back mode ................................................................................... 40
HOST MODE SERIAL INTERFACE OPERATION ........................................................... 41
USING THE MICROPROCESSOR SERIAL INTERFACE ...................................................................................... 41
Figure 25. Microprocessor Serial Interface Data Structure ................................................................ 42
TABLE 16: MICROPROCESSOR REGISTER ADDRESS ................................................................................... 43
TABLE 17: MICROPROCESSOR REGISTER BIT MAP ..................................................................................... 43
TABLE 18: MICROPROCESSOR REGISTER #0 BIT DESCRIPTION .................................................................... 45
TABLE 19: MICROPROCESSOR REGISTER #1 BIT DESCRIPTION .................................................................... 46
TABLE 20: MICROPROCESSOR REGISTER #2 BIT DESCRIPTION .................................................................... 48
TABLE 21: MICROPROCESSOR REGISTER #3 BIT DESCRIPTION .................................................................... 50
TABLE 22: MICROPROCESSOR REGISTER #4 BIT DESCRIPTION .................................................................... 52
TABLE 23: MICROPROCESSOR REGISTER #5 BIT DESCRIPTION .................................................................... 53
TABLE 24: MICROPROCESSOR REGISTER #6 BIT DESCRIPTION .................................................................... 55
TABLE 25: MICROPROCESSOR REGISTER #7 BIT DESCRIPTION .................................................................... 56
TABLE 26: MICROPROCESSOR REGISTER #8 BIT DESCRIPTION .................................................................... 56
TABLE 27: MICROPROCESSOR REGISTER #9 BIT DESCRIPTION .................................................................... 57
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