XRT83L30 Datasheet, PDF (45/78 Pages) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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XRT83L30
ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.0
Bit 2 through 6:The five (5) Address Values (labeled A0, A1, A2, A3 and A4)
The next five rising edges of the SCLK signal, clock in the 5-bit address value for the Read or Write operation.
These five bits define the register address within XRT83L30 that the user has selected to read data from or
write data to. The address bits must be supplied to the SDI input in ascending order with LSB (Least Significant
Bit) first.
Bit 7: (A5)
The next bit A5 must be set to “0” as shown in Figure 25.
Bit 8: (A6)
The value of A6 is a “don’t care”.
Once the first eight bits have been written into the Serial interface, the subsequent action depends on the
whether the current operation is a “Read” or “Write” instruction.
Read Operation
With the last address bit “A4” written into the SDI input, the “Read” operation will proceed through an idle
period lasting two SCLK periods. On the rising edge of the 9th SCLK the serial data output (SDO) becomes
active (see Figure 25). At this point the user can begin reading the 8-bit data (D0 through D7) stored in the
interface register at address [A4,A3,A2,A1,A0], in ascending order (LSB first), on the falling edge of SCLK.
Write Operation
With the last address bit (A4) written into the SDI input, the “Write” operation will proceed through an idle
period lasting two SCLK periods. Prior to the rising edge of the 9th SCLK, the user must begin to apply the
eight bit data word to the SDI input. The Serial Interface will latch this data on the rising edge of SCLK. The
serial data (D0 through D7) should enter the SDI input in ascending order with the LSB first.
Serial Interface Register Description
The serial Interface consists of 32 8-bit register locations. The Microprocessor register address map and Bit
map are described in Table 16 and Table 17 respectively. The function of the individual bits are described in
Table 18 through Table 36.
FIGURE 25. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
CS
SCLK
SDI
SDO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
R/W Ao A1 A2 A3 A4 0 A6 D0 D1 D2 D3 D4 D5 D6 D7
High Z
High Z
D0 D1 D2 D3 D4 D5 D6 D7
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