XRT83L30 Datasheet, PDF (13/78 Pages) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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XRT83L30
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.0
SIGNAL NAME
CLKSEL2
CLKSEL1
CLKSEL0
PIN #
17
18
19
TYPE
I
DESCRIPTION
Clock Select input for Master Clock Synthesizer pin 2
Clock Select input for Master Clock Synthesizer pin 1
Clock Select input for Master Clock Synthesizer pin 0
In Hardware mode, CLKSEL[2:0] are input signals to a programmable fre-
quency synthesizer that can be used to generate a master clock from an
external accurate clock source according to the following table. The
MCLKRATE control signal is generated from the state of EQC[4:0] inputs.
See Table 5 for description of Transmit Equalizer Control bits.
In Host mode, the state of these pins are ignored and the master frequency
PLL is controlled by the corresponding interface bits.
MCLKE1 MCLKT1
(kHz)
(kHz)
2048
2048
2048
2048
2048
1544
1544
1544
1544
1544
2048
1544
8
X
8
X
16
X
16
X
56
X
56
X
64
X
64
X
128
X
128
X
256
X
256
X
CLKSEL2 CLKSEL1 CLKSEL0 MCLKRATE
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
CLKOUT
(KHz)
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
NOTE: Internally pulled "Low" with a 50kΩ resistor.
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