XRT83L30 Datasheet, PDF (51/78 Pages) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

áç
XRT83L30
ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.0
TABLE 20: MICROPROCESSOR REGISTER #2 BIT DESCRIPTION
REGISTER ADDRESS
00010
BIT #
NAME
FUNCTION
REGISTER RESET
TYPE VALUE
D7
RXON Receiver ON: Writing a “1” into this bit location turns on the
R/W
0
Receive Section. Writing a “0” shuts off the Receiver Section. In
this mode, RTIP and RRING driver outputs will be tri-stated for
power reduction or redundancy applications. Default is "0", off.
D6
TXTEST2 Transmit Test Pattern bit 2: This bit together with TXTEST1 and R/W
0
TXTEST0 are used to generate and transmit test patterns
according to the following table:
TXTEST2
0
0
0
0
1
1
1
1
TXTEST1
0
0
1
1
0
0
1
1
TXTEST0
Test Pattern
0
Transmit Data
1
TAOS
0
TLUC
1
TLDC
0
TDQRSS
1
TDQRSS & INVQRSS
0
TDQRSS & INSBER
1
TDQRSS & INVQRSS & INSBER
TDQRSS (Transmit/Detect Quasi-Random Signal): This con-
dition, when activated, enables Quasi-Random Signal Source
generation and detection. In a T1 system QRSS pattern is a 2²⁰-
1 pseudo-random bit sequence (PRBS) with no more than 14
consecutive zeros. In a E1 system, QRSS is a 2¹⁵-1 PRBS pat-
tern.
TAOS (Transmit All Ones): Activating this condition enables the
transmission of an All Ones Pattern. TCLK must not be tied
"Low".
TLUC (Transmit Network Loop-Up Code): Activating this con-
dition enables the Network Loop-Up Code of "00001" to be trans-
mitted to the line. When Network Loop-Up code is being
transmitted, the XRT83L30 will ignore the Automatic Loop-Code
detection and Remote Loop-Back activation (NLCDE1 =“1”,
NLCDE0 =“1”, if activated) in order to avoid activating Remote
Digital Loop-Back automatically when the remote terminal
responds to the Loop-Back request.
TLDC (Transmit Network LOOP-Down Code): Activating this
condition enables the network Loop-Down Code of "001" to be
transmitted to the line.
D5
TXTEST1 Transmit Test pattern bit 1: See description of bit D6 for the
R/W
0
function of this bit.
48