XRT83L30 Datasheet, PDF (65/78 Pages) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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XRT83L30
ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.0
TABLE 35: MICROPROCESSOR REGISTER #17 BIT DESCRIPTION
REGISTER ADDRESS
10001
BIT #
NAME
FUNCTION
REGISTER RESET
TYPE VALUE
D7
Reserved
R/W
0
D6
CLKSEL2 Clock Select Inputs for Master Clock Synthesizer bit 2: In
R/W
0
Host mode, CLKSEL[2:0] are input signals to a programmable
frequency synthesizer that can be used to generate a master
clock from an external accurate clock source according to the fol-
lowing table:
MCLKE1 MCLKT1
kHz
kHz
2048
2048
2048
2048
2048
1544
1544
1544
1544
1544
2048
1544
8
X
8
X
16
X
16
X
56
X
56
X
64
X
64
X
128
X
128
X
256
X
256
X
CLKSEL2 CLKSEL1 CLKSEL0 MCLKRATE
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
CLKOUT
kHz
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
In Hardware mode the state of these bits are ignored and the
master frequency PLL is controlled by the corresponding Hard-
ware pins.
D5
CLKSEL1 Clock Select inputs for Master Clock Synthesizer bit 1: See R/W
0
description of bit D6 for function of this bit.
D4
CLKSEL0 Clock Select inputs for Master Clock Synthesizer bit 0: See R/W
0
description of bit D6 for function of this bit.
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