XRT83L30 Datasheet, PDF (24/78 Pages) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L30
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ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.3.0
PRELIMINARY
The total cable loss at RLOS declaration is typically -52dB (-43dB + -9dB). A 3dB hysteresis was designed so
that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a total cable
attenuation of -49dB. See Figure 9 for a simplified diagram.
FIGURE 9. SIMPLIFIED DIAGRAM OF EXTENDED RLOS MODE (E1 ONLY)
+3dB
-9dB
Normalized up to +45dB Max
Clear LOS
Declare LOS
+3dB
-9dB
Declare LOS
Clear LOS
Normalized up to +45dB Max
RECEIVE HDB3/B8ZS DECODER
The Decoder function is available in both Hardware and Host modes by controlling the TNEG/CODE pin or the
CODE interface bit. The decoder function is only active in single-rail Mode. When selected, receive data in this
mode will be decoded according to HDB3 rules for E1 and B8ZS for T1 systems. Bipolar violations that do not
conform to the coding scheme will be reported as Line Code Violation at the RNEG/LCV pin. The length of the
LCV pulse is one RCLK cycle for each code violation. Excessive number of zeros in the receive data stream is
also reported as an error at the same output pin. If AMI decoding is selected in single rail mode, every bipolar
violation in the receive data stream will be reported as an error at the RNEG/LCV pin.
RECOVERED CLOCK (RCLK) SAMPLING EDGE
This feature is available in both Hardware and Host modes. In Host mode, the sampling edge of RCLK output
can be changed through the interface control bit RCLKE. If a “1” is written in the RCLKE interface bit, receive
data output at RPOS/RDATA and RNEG/LCV are updated on the falling edge of RCLK. Writing a “0” to the
RCLKE register, updates the receive data on the rising edge of RCLK. In Hardware mode the same feature is
available under the control of the RCLKE pin.
FIGURE 10. RECEIVE CLOCK AND OUTPUT DATA TIMING
R_DY
RCLK_R
RCLK_F
RCLK
RPOS
or
RNEG
R_HO
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