XRT83L30 Datasheet, PDF (56/78 Pages) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L30
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ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.3.0
PRELIMINARY
TABLE 23: MICROPROCESSOR REGISTER #5 BIT DESCRIPTION
REGISTER ADDRESS
00101
BIT #
NAME
FUNCTION
REGISTER RESET
TYPE VALUE
D7
Reserved
RO
0
D6
DMO
Driver Monitor Output: This bit is set to a "1" to indicate trans-
RO
0
mit driver failure is detected. The value of this bit is based on the
current status of DMO. If the DMOIE bit is enabled, any transition
on this bit will generate an Interrupt.
D5
FLS
FiFO Limit Status: This bit is set to a "1" to indicate that the jitter RO
0
attenuator read/write FIFO pointers are within +/- 3 bits. If the
FLSIE bit is enabled, any transition on this bit will generate an
Interrupt.
D4
LCV
Line Code Violation: This bit is set to a "1" to indicate that the
RO
0
receiver is currently detecting a Line Code Violation or an exces-
sive number of zeros in the B8ZS or HDB3 modes. If the LCVIE
bit is enabled, any transition on this bit will generate an Interrupt.
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