XRT83L30 Datasheet, PDF (55/78 Pages) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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XRT83L30
ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.0
REGISTER ADDRESS
00100
BIT #
D7
D6
D5
D4
D3
D2
D1
D0
TABLE 22: MICROPROCESSOR REGISTER #4 BIT DESCRIPTION
NAME
GIE
DMOIE
FLSIE
LCVIE
NLCDIE
AISDIE
RLOSIE
QRPDIE
FUNCTION
REGISTER RESET
TYPE VALUE
Global Interrupt Enable: Writing a "1" into this bit, globally
R/W
0
enables interrupt generation on the INT pin. Writing a "0" into this
bit, globally masks all interrupt requests.
DMO Interrupt Enable: Writing a "1" to this bit enables DMO
R/W
0
interrupt generation, writing a "0" masks it.
FIFO Limit Status Interrupt Enable: Writing a "1" to this bit
R/W
0
enables interrupt generation when the FIFO limit is within 3 bits,
writing a "0" to masks it.
Line Code Violation Interrupt Enable: Writing a "1" to this bit
R/W
0
enables Line Code Violation interrupt generation, writing a "0"
masks it.
Network Loop-Code Detection Interrupt Enable: Writing a "1" R/W
0
to this bit enables Network Loop-code detection interrupt genera-
tion, writing a "0" masks it.
AIS Detection Interrupt Enable: Writing a "1" to this bit enables R/W
0
Alarm Indication Signal detection interrupt generation, writing a
"0" masks it.
Receive Loss of Signal Interrupt Enable: Writing a "1" to this R/W
0
bit enables Loss of Receive Signal interrupt generation, writing a
"0" masks it.
QRSS Pattern Detection Interrupt Enable: Writing a "1" to this R/W
0
bit enables QRSS pattern detection interrupt generation, writing
a "0" masks it.
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