XRT83L30 Datasheet, PDF (64/78 Pages) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L30
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ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.3.0
PRELIMINARY
TABLE 34: MICROPROCESSOR REGISTER #16 BIT DESCRIPTION
REGISTER ADDRESS
10000
BIT #
NAME
FUNCTION
REGISTER RESET
TYPE VALUE
D7
SR/DR Single-rail/Dual-rail Select: Writing a "1" to this bit configures
R/W
0
the XRT83L30 to operate in the Single-rail mode.
Writing a "0" configures the XRT83L30 to operate in Dual-rail
mode.
D6
ATAOS Automatic Transmit All Ones Upon RLOS: Writing a "1" to this R/W
0
bit enables the automatic transmission of All Ones data to the
line.
Writing a "0" disables this feature.
D5
RCLKE Receive Clock Edge: Writing a "1" to this bit selects receive out- R/W
0
put data to be updated on the negative edge of RCLK.
Writing a "0" selects data to be updated on the positive edge of
RCLK.
D4
TCLKE Transmit Clock Edge: Writing a "0" to this bit selects transmit
R/W
0
data at TPOS/TDATA and TNEG to be sampled on the falling
edge of TCLK.
Writing a "1" selects the rising edge of the TCLK for sampling.
D3
DATAP DATA Polarity: Writing a "0" to this bit selects transmit input and R/W
0
receive output data of the XRT83L30 to be active "High".
Writing a "1" selects an active "Low" state.
D2
Reserved
R/W
0
D1
Reserved
R/W
0
D0
SRESET Software Reset µP Registers: Writing a "1" to this bit longer
R/W
0
than 10µs resets all internal state machines
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