XRT83L30 Datasheet, PDF (77/78 Pages) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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XRT83L30
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.0
ORDERING INFORMATION
PART #
XRT83L30IV
THERMAL INFORMATION
PACKAGE
64 Pin TQFP
Theta - J_A = 38° C/W
OPERATING TEMPERATURE RANGE
-40^oC to +85^oC
Theta J_C = 7° C/W
REVISION HISTORY
Rev. A1.0.0 Advanced version.
Rev. P1.1.0 Preliminary release.
Rev. P1.2.0 Modified microprocessor tables, moved various functions. Added GHCI_n, SL_1, SL_0, EQG_1
EQG_0, GAUGE1 and GAUGE0 to Control Global Register 18. Separated Microprocessor description table by
register number. Moved absolute maximum and DC electrical characteristics before AC electrical characteris-
tics. Replaced TBD’s in electrical ables. Reformated table of contents.
Rev. P1.2.1 Renamed FIFO pin to GAUGE, edited definition and edited defintion of JASEL[1:0] to reflect the
FIFO size is selected by the jitter attenuator select.
Rev. P1.2.2 Redefined bits D3, D2 and D0 of register 1, in combination these bits set the jitter attenuator path
and FIFO size.
Rev. P1.2.3 Added definitions to dual function pins in the pin description section.
Rev P1.2.4 Added JABW, JASEL1 and JASEL0 table in pin list and Jitter attenuator section. Corrected typos in
features, figures 7, 8, 9 and 11. Added Jitter attenuator tables in microprocessor register tables.
Rev. P1.2.5 Table 18, 23, 24, 25 change GCHIE to GIE, GHCI and GCHIS to Reserved. Corrected package
outline drawing.
Rev. P1.2.6 TERCNTL (pin 46) function removed. Bit 7 of Microprocessor Register #2 was INSBER, is now re-
served. Bit 1 of Microprocessor Register #3 was INVQRSS, is now reserved. New description for bits D6 - D0
in Tables 27 - 34 Microprocessor Registers.
Rev. P1.2.7 Expanded information on Receive Redundancy. 2 tables and 1 figure.
Rev. P1.2.8 Edited section on RLOS
Rev. P1.2.9 Removed TERCNTL from block diagram. Edit EQC[4:0] to be input only on block diagram. Cor-
rected RXMUTE, TCLK, JABW, MCKLE1, CLKSEL [2:0], RXTSEL, TERSEL[1:0], RXRES[1:0], ATAOS, NLCD
in the pin descriptions section. Replaced the Functional Description section. Edits to Table 18: Microproces-
sor Register Bit Map, Table 21: Microprocessor Register #2 Bit Description, Table 35: Microprocessor Register
#16 Bit Description
Rev. P1.3.0 Table 35: Microprocessor Register #17 Bit Description, edit E1 clock MCLKRATE= “0” and T1/J1
clock MCLKRATE=”1” .
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