XRT83L30 Datasheet, PDF (57/78 Pages) Exar Corporation – SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

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XRT83L30
ONE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.0
TABLE 23: MICROPROCESSOR REGISTER #5 BIT DESCRIPTION
D3
NLCD Network Loop-Code Detection:
RO
0
This bit operates differently in the Manual or the Automatic Net-
work Loop-Code detection modes.
In the Manual Loop-Code detection mode (NLCDE1 =”0” and
NLCDE0 =”1”, or NLCDE1 =”1” and NLCDE0 =”0”) this bit gets
set to “1” as soon as the Loop-Up (“00001”) or Loop-Down
(“001”) code is detected in the receive data for longer than 5 sec-
onds. The NLCD bit stays in the “1” state for as long as the chip
detects the presence of the Loop-Code in the receive data and it
is reset to “0” as soon as it stops receiving it. In this mode if the
NLCD interrupt is enabled the chip will initiate an interrupt on
every transition of the NLCD.
When the Automatic Loop-Code detection mode (NLCDE1 =”1”
and NLCDE0 =”1”) is initiated, the state of the NLCD interface bit
is reset to “0” and the chip is programmed to monitor the receive
input data for the Loop-Up Code. This bit is set to a “1” to indicate
that the Network Loop Code is detected for more than 5 seconds.
Simultaneously the Remote Loop-Back condition is automatically
activated and the chip is programmed to monitor the receive data
for the Network Loop-Down Code. The NLCD bit stays in the “1”
state for as long as the Remote Loop-Back condition is in effect
even if the chip stops receiving the Loop-Up Code. Remote
Loop-Back is removed if the chip detects the “001” pattern for
longer than 5 seconds in the receive data. Detecting the “001”
pattern also results in resetting the NLCD interface bit and initiat-
ing an interrupt provided the NLCD interrupt enable bit it active.
When programmed in the Automatic detection mode, the NLCD
interface bit stays “High” for the entire time the Remote Loop-
Back is active and initiates an interrupt anytime the status of the
NLCD bit changes. In this mode the host can monitor the state of
the NLCD bit to determine if the Remote Loop-Back is activated.
D2
AISD Alarm Indication Signal Detect: This bit is set to a "1" to indi-
RO
0
cate All Ones Signal is detected by the receiver. The value of this
bit is based on the current status of Alarm Indication Signal
detector. If the AISDIE bit is enabled, any transition on this bit will
generate an Interrupt.
D1
RLOS Receive Loss of Signal: This bit is set to a "1" to indicate that
RO
0
the receive input signal is lost. The value of this bit is based on
the current status of the receive input signal. If the RLOSIE bit is
enabled, any transition on this bit will generate an Interrupt.
D0
QRPD Quasi-random Pattern Detection: This bit is set to a "1" to indi- RO
0
cate the receiver is currently in synchronization with QRSS pat-
tern. The value of this bit is based on the current status of Quasi-
random pattern detector of. If the QRPDIE bit is enabled, any
transition on this bit will generate an Interrupt.
54