LM3S6950 Datasheet, PDF (84/524 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
Register 14: Device Capabilities 1 (DC1), offset 0x010
This register is predefined by the part and can be used to verify features. The PWM, SARADC0,
MAXADCSPD, WDT, SWO, SWD, and JTAG bits mask the RCGC0, SCGC0, and DCGC0 registers.
Other bits are passed as 0. MAXADCSPD is clipped to the maximum value specified in DC1.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0010.30DF
31
30
29
28
Type RO
RO
RO
RO
Reset
0
0
0
0
15
14
13
12
SYSDIV
Type RO
RO
RO
RO
Reset
0
0
1
1
27
26
25
reserved
RO
RO
RO
0
0
0
11
10
9
reserved
RO
RO
RO
0
0
0
24
23
22
21
20
19
18
17
16
PWM
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
1
0
0
0
0
8
7
6
5
4
3
2
1
0
MPU
HIB reserved PLL
WDT SWO SWD JTAG
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
1
1
0
1
1
1
1
1
Bit/Field
31:21
20
19:16
15:12
Name
reserved
PWM
reserved
SYSDIV
Type
RO
RO
RO
RO
Reset
0
1
0
0x3
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
When set, indicates that the PWM module is present.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Value Description
0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4.
11:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
MPU
RO
1
When set, indicates that the Cortex-M3 Memory Protection Unit (MPU)
module is present. See the ARM Cortex-M3 Technical Reference Manual
for details on the MPU.
6
HIB
RO
1
When set, indicates that the Hibernation module is present.
5
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
PLL
RO
1
When set, indicates that the on-chip Phase Locked Loop (PLL) is
present.
3
WDT
RO
1
When set, indicates that a watchdog timer is present.
84
June 14, 2007
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