LM3S6950 Datasheet, PDF (15/524 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S6950 Microcontroller
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Register 24:
Register 25:
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 270
UART Control (UARTCTL), offset 0x030 ......................................................................... 272
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 274
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 275
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 277
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 278
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 279
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 281
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 282
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 283
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 284
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 285
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 286
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 287
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 288
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 289
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 290
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 291
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 292
SSI ................................................................................................................................................. 293
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 305
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 307
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 309
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 310
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 311
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 312
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 313
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 314
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 315
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 316
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 317
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 318
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 319
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 320
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 321
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 322
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 323
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 324
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 325
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 326
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 327
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 328
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 342
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 343
Register 3: I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 347
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 348
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 349
Register 6: I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 350
June 14, 2007
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