LM3S6950 Datasheet, PDF (469/524 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S6950 Microcontroller
20
Signal Tables
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register.
Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7
and PC[3:0]) which default to the JTAG functionality.
Table 20-1 on page 469 shows the pin-to-signal-name mapping, including functional characteristics
of the signals. Table 20-2 on page 473 lists the signals in alphabetical order by signal name.
Table 20-3 on page 478 groups the signals by functionality, except for GPIOs. Table 20-4 on page
482 lists the GPIO pins and their alternate functionality.
Table 20-1. Signals by Pin Number
Pin Number
1
2
3
Pin Name
PE7
PWM5
PE6
PWM4
VDDA
Pin Type
I/O
O
I/O
O
-
4
GNDA
-
5
PE5
I/O
6
CCP3
I/O
PE4
I/O
7
LDO
-
8
VDD
-
9
GND
-
10
PD0
I/O
PWM0
O
11
PD1
I/O
PhA0
I
12
PD2
I/O
U1Rx
I
Buffer Type Description
TTL
GPIO port E bit 7
TTL
PWM 5
TTL
GPIO port E bit 6
TTL
PWM 4
Power
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
Power
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
TTL
GPIO port E bit 5
TTL
Capture/Compare/PWM 3
TTL
GPIO port E bit 4
Power
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 µF or greater. When the
on-chip LDO is used to provide power to the
logic, the LDO pin must also be connected to
the VDD25 pins at the board level in addition
to the decoupling capacitor(s).
Power Positive supply for I/O and some logic.
Power Ground reference for logic and I/O pins.
TTL
GPIO port D bit 0
TTL
PWM 0
TTL
GPIO port D bit 1
TTL
QEI module 0 Phase A
TTL
GPIO port D bit 2
TTL
UART module 1 receive. When in IrDA mode,
this signal has IrDA modulation.
June 14, 2007
469
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