LM3S6950 Datasheet, PDF (367/524 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S6950 Microcontroller
write. For the MAC module core, data sent/received can be larger than 1500 bytes, and no Frame
Too Long error is reported. Instead, a FIFO Overrun error is reported when the frame received
is too large to fit into the Ethernet controller’s RAM.
■ Frame Check Sequence (FCS)
The frame check sequence carries the CRC (cyclic redundancy check value). The value of this
field is computed over destination address, source address, length/type, data, and pad fields
using the CRC-32 algorithm. The MAC module computes the FCS value one nibble at a time.
For transmitted frames, this field is automatically inserted by the MAC layer, unless disabled by
the CRC bit in the MACTCTL register. For received frames, this field is automatically checked.
If the FCS does not pass, the frame will not be placed in the RX FIFO, unless the FCS check is
disabled by the BADCRC bit in the MACRCTL register.
15.2.3.2 MAC Layer FIFOs
For Ethernet frame transmission, a 2K Byte TX FIFO is provided that can be used to store a single
frame. While the IEEE 802.3 specification limits the size of an Ethernet frame's payload section to
1500 Bytes, the Ethernet controller places no such limit. The full buffer can be used, for a paylload
of up to 2032 bytes.
For ethernet frame reception, a 2K Byte RX FIFO is provided that can be used to store multiple
frames, up to a maximum of 31 frames. If a frame is received and there is insufficient space in the
RX FIFO, an overflow error will be indicated.
For details regarding the TX and RX FIFO layout, refer to Table 15-1 on page 367. Please note the
following difference between TX and RX FIFO layout. For the TX FIFO, the Data Length field in the
first FIFO word refers to the Ethernet frame data payload, as shown in the 5th to nth FIFO positions.
For the RX FIFO, the Frame Lenth field is the total length of the receieved ethernet frame, including
the FCS and Frame Length bytes. Also note that if FCS generation is disabled with the CRC bit in
the MACTCTL register, the last word in the FIFO must be the FCS bytes for the frame that has been
written to the FIFO.
Also note that if the length of the data payload section is not a multiple of 4, the FCS field will overlap
words in the FIFO. However, for the RX FIFO, the beginning of the next frame will always be on a
word boundary.
Table 15-1. TX & RX FIFO Organization
FIFO Word Read/Write
Sequence
1st
2nd
3rd
Word Bit Fields
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
TX FIFO (Write)
Data Length LSB
Data Length MSB
RX FIFO (Read)
Frame Length LSB
Frame Length MSB
DA oct 1
DA oct 2
DA oct 3
DA oct 4
DA oct 5
DA oct 6
SA oct 1
SA oct 2
SA oct 3
SA oct 4
June 14, 2007
367
Luminary Micro Confidential-Advance Product Information