LM3S6950 Datasheet, PDF (75/524 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S6950 Microcontroller
Bit/Field
19:17
16:14
13
12
11
10
9:6
5:4
Name
PWMDIV
reserved
PWRDN
reserved
BYPASS
reserved
XTAL
OSCSRC
Type
R/W
RO
R/W
RO
R/W
RO
R/W
R/W
Reset
0x7
Description
PWM Unit Clock Divisor
This field specifies the binary divisor used to predivide the system clock
down for use as the timing reference for the PWM module. This clock
is only power 2 divide and rising edge is synchronous without phase
shift from the system clock.
Binary Value Divisor
000
/2
001
/4
010
/8
011
/16
100
/32
101
/64
110
/64
111
/64 (default)
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL.
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
PLL Bypass
Chooses whether the system clock is derived from the PLL output or
the OSC source. If set, the clock that drives the system is the OSC
source. Otherwise, the clock that drives the system is the PLL output
clock divided by the system divider.
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0xB
This field specifies the crystal value attached to the main oscillator. The
encoding for this field is provided in Table 6-3 on page 76.
0x1
Picks among the four input sources for the OSC. The values are:
Value Input Source
00 Main oscillator (default)
01 Internal oscillator (default)
10 Internal oscillator / 4 (this is necessary if used as input to PLL)
11 reserved
June 14, 2007
75
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