LM3S6950 Datasheet, PDF (374/524 Pages) List of Unclassifed Manufacturers – Microcontroller

Ethernet Controller
Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000
A write of a 1 to any bit position of this register clears the corresponding interrupt bit in the Ethernet
MAC Raw Interrupt Status (MACRIS) register.
Ethernet MAC Interrupt Acknowledge (MACIACK)
Base 0x4004.8000
Offset 0x000
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
Type RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
15
14
13
12
11
10
9
reserved
Type RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
24
23
reserved
RO
RO
0
0
8
7
RO
RO
0
0
22
21
20
19
18
17
16
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
6
5
4
3
2
1
0
MDINT RXER FOV TXEMP TXER RXINT
RO
W1C W1C W1C W1C W1C W1C
0
0
0
0
0
0
0
Bit/Field
31:6
6
5
4
3
2
1
0
Name
reserved
PHYINT
MDINT
RXER
FOV
TXEMP
TXER
RXINT
Type
RO
W1C
W1C
W1C
W1C
W1C
W1C
W1C
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
A write of a 1 to the PHYINT bit clears the PHYINT interrupt read from
the MACRIS register.
A write of a 1 to the MDINT bit clears the MDINT interrupt read from the
MACRIS register.
A write of a 1 to the RXER bit clears the RXER interrupt read from the
MACRIS register.
A write of a 1 to the FOV bit clears the FOV interrupt read from the
MACRIS register.
A write of a 1 to the TXEMP bit clears the TXEMP interrupt read from
the MACRIS register.
A write of a 1 to the TXER bit clears the TXER interrupt read from the
MACRIS register and resets the TX FIFO write pointer.
A write of a 1 to the RXINT bit clears the RXINT interrupt read from the
MACRIS register.
374
June 14, 2007
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