LM3S6950 Datasheet, PDF (207/524 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S6950 Microcontroller
10.3.6
Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained
by reading the GPTM Timern (GPTMTnR) register.
In Input Edge Timing mode, the timer continues running after an edge event has been detected,
but the timer interval can be changed at any time by writing the GPTMTnILR register. The change
takes effect at the next cycle after the write.
16-Bit PWM Mode
A timer is configured to PWM mode using the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnEVENT field
of the GPTM Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes
effect at the next cycle after the write.
10.4
Register Map
Table 10-2 on page 207 lists the GPTM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that timer’s base address:
■ Timer0: 0x4003.0000 0x4003.0000
■ Timer1: 0x4003.1000 0x4003.1000
■ Timer2: 0x4003.2000 0x4003.2000
■ Timer3: 0x4003.3000 0x4003.3000
Table 10-2. Timers Register Map
Offset Name
Type
Reset
Description
0x000 GPTMCFG
0x004 GPTMTAMR
0x008 GPTMTBMR
0x00C GPTMCTL
R/W
0x0x0000.0000 GPTM Configuration
R/W
0x0x0000.0000 GPTM TimerA Mode
R/W
0x0x0000.0000 GPTM TimerB Mode
R/W
0x0x0000.0000 GPTM Control
See
page
209
210
211
212
June 14, 2007
207
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