LM3S6950 Datasheet, PDF (130/524 Pages) List of Unclassifed Manufacturers – Microcontroller

Hibernation Module
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020
This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources.
Hibernation Interrupt Clear (HIBIC)
Offset 0x020
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
EXTW LOWBAT RTCALT1 RTCALT0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO R/W1C R/W1C R/W1C R/W1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
2
1
0
Name
reserved
EXTW
LOWBAT
RTCALT1
RTCALT0
Type
Reset Description
RO 0x000.0000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W1C
0
External Wake-Up Masked Interrupt Clear
Reads return an indeterminate value.
R/W1C
0
Low Battery Voltage Masked Interrupt Clear
Reads return an indeterminate value.
R/W1C
0
RTC Alert1 Masked Interrupt Clear
Reads return an indeterminate value.
R/W1C
0
RTC Alert0 Masked Interrupt Clear
Reads, return an indeterminate value.
130
June 14, 2007
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