LM3S6950 Datasheet, PDF (438/524 Pages) List of Unclassifed Manufacturers – Microcontroller

Pulse Width Modulator (PWM)
Register 13: PWM0 Interrupt Enable (PWM0INTEN), offset 0x044
Register 14: PWM1 Interrupt Enable (PWM1INTEN), offset 0x084
Register 15: PWM2 InterruptEnable (PWM2INTEN), offset 0x0C4
These registers control the interrupt generation capabilities of the PWM generators (PWM0INTEN
controls the PWM generator 0 block, and so on). The events that can cause an interrupt are:
■ The counter being equal to the load register
■ The counter being equal to zero
■ The counter being equal to the comparator A register while counting up
■ The counter being equal to the comparator A register while counting down
■ The counter being equal to the comparator B register while counting up
■ The counter being equal to the comparator B register while counting down
Any combination of these events can generate either an interrupt.
PWM0 Interrupt Enable (PWM0INTEN)
Base 0x4002.8000
Offset 0x044
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:6
5
4
3
2
1
0
Name
reserved
IntCmpBD
IntCmpBU
IntCmpAD
IntCmpAU
IntCntLoad
IntCntZero
Type
RO
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
When 1, an interrupt occurs when the counter matches the comparator B
value and the counter is counting down.
When 1, an interrupt occurs when the counter matches the comparator B
value and the counter is counting up.
When 1, an interrupt occurs when the counter matches the comparator A
value and the counter is counting down.
When 1, an interrupt occurs when the counter matches the comparator A
value and the counter is counting up.
When 1, an interrupt occurs when the counter matches the PWMnLOAD
register.
When 1, an interrupt occurs when the counter is 0.
438
June 14, 2007
Luminary Micro Confidential-Advance Product Information