LM3S6950 Datasheet, PDF (279/524 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S6950 Microcontroller
Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x044
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
OEIC BEIC PEIC FEIC RTIC TXIC RXIC
reserved
Type RO
RO
RO
RO
RO
W1C W1C W1C W1C W1C W1C W1C
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:11
10
9
8
7
6
5
Name
reserved
OEIC
BEIC
PEIC
FEIC
RTIC
TXIC
Type
RO
W1C
W1C
W1C
W1C
W1C
W1C
Reset
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Overrun Error Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
Break Error Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
Parity Error Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
Framing Error Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
Receive Time-Out Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
Transmit Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
June 14, 2007
279
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