LM3S6950 Datasheet, PDF (16/524 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 351
I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 352
I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 353
I²C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 355
I²C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 356
I²C Slave Data (I2CSDR), offset 0x008 ........................................................................... 358
I²C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 359
I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 360
I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 361
I²C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 362
Ethernet ........................................................................................................................................ 363
Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000 ............................................ 372
Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000 ....................................... 374
Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 375
Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 376
Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 377
Register 6: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 378
Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 379
Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 380
Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 381
Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 382
Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 383
Register 12: Ethernet MAC Management Address (MACMADD), offset 0x028 ...................................... 384
Register 13: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 385
Register 14: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 386
Register 15: Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 387
Register 16: Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 388
Register 17: Ethernet PHY Management Register 0 – Control (MR0), offset 0x00 ................................. 389
Register 18: Ethernet PHY Management Register 1 – Status (MR1), offset 0x01 .................................. 391
Register 19: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), offset 0x02 .................... 393
Register 20: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), offset 0x03 .................... 394
Register 21: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), offset
0x04 ............................................................................................................................. 395
Register 22: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), offset 0x05 ......................................................................................................... 397
Register 23: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), offset
0x06 ............................................................................................................................. 398
Register 24: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), offset 0x10 ................. 399
Register 25: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), offset 0x11 ...... 401
Register 26: Ethernet PHY Management Register 18 – Diagnostic (MR18), offset 0x12 ........................ 403
Register 27: Ethernet PHY Management Register 19 – Transceiver Control (MR19), offset 0x13 ........... 404
Register 28: Ethernet PHY Management Register 23 – LED Configuration (MR23), offset 0x17 ............. 405
Register 29: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), offset 0x18 .............. 406
Analog Comparators ................................................................................................................... 407
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 413
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 414
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 415
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 416
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June 14, 2007
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