LM3S6950 Datasheet, PDF (41/524 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S6950 Microcontroller
3 Memory Map
The memory map for the LM3S6950 controller is provided in Table 3-1 on page 41.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
Note: In Table 3-1 on page 41 addresses not listed are reserved.
Table 3-1. Memory Map^a
Start
End
Memory
0x0000.0000
0x2000.0000
0x2010.0000
0x2200.0000
0x2400.0000
FiRM Peripherals
0x4000.0000
0x4000.1000
0x4000.4000
0x4000.5000
0x4000.6000
0x4000.7000
0x4000.8000
0x4000.9000
0x4000.A000
0x4000.C000
0x4000.D000
0x4000.E000
0x4000.F000
0x4001.0000
Peripherals
0x4002.0000
0x4002.0800
0x4002.2000
0x4002.4000
0x4002.5000
0x4002.6000
0x4002.8000
0x4002.9000
0x4002.C000
0x1FFF.FFFF
0x200F.FFFF
0x21FF.FFFF
0x23FF.FFFF
0x3FFF.FFFF
0x4000.0FFF
0x4000.3FFF
0x4000.4FFF
0x4000.5FFF
0x4000.6FFF
0x4000.7FFF
0x4000.8FFF
0x4000.9FFF
0x4000.BFFF
0x4000.CFFF
0x4000.DFFF
0x4000.EFFF
0x4000.FFFF
0x4001.FFFF
0x4002.07FF
0x4002.0FFF
0x4002.3FFF
0x4002.4FFF
0x4002.5FFF
0x4002.6FFF
0x4002.8FFF
0x4002.BFFF
0x4002.CFFF
Description
For details
on
registers,
see page ...
On-chip flash ^b
137
Bit-banded on-chip SRAM^c
137
Reserved non-bit-banded SRAM space
-
Bit-band alias of 0x2000.0000 through 0x200F.FFFF 133
Reserved non-bit-banded SRAM space
-
Watchdog timer
232
Reserved
-
GPIO Port A
162
GPIO Port B
162
GPIO Port C
162
GPIO Port D
162
SSI0
304
SSI1
304
Reserved
-
UART0
260
UART1
260
UART2
260
Reserved
-
Reserved for future FiRM peripherals
-
I2C Master 0
341
I2C Slave 0
354
Reserved
-
GPIO Port E
162
GPIO Port F
162
GPIO Port G
162
PWM
427
Reserved
-
QEI0
455
June 14, 2007
41
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