LM3S6950 Datasheet, PDF (365/524 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S6950 Microcontroller
For the MII management interface to function properly, the internal clock must be divided down from
the system clock to a frequency no greater than 2.5 MHz. The MACMDV register contains the divider
used for scaling down the system clock. See page 383 for more details about the use of this register.
15.2.2
PHY Configuration/Operation
The Physical Layer (PHY) in the Ethernet controller includes integrated ENDECs,
scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions.
The transmitter includes an on-chip pulse shaper and a low-power line driver. The receiver has an
adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery.
The transceiver interfaces to Category-5 unshielded twisted pair (Cat-5 UTP) cabling for 100BASE-TX
applications, and Category-3 unshielded twisted pair (Cat-3 UTP) for 10BASE-T applications. The
Ethernet Controller is connected to the line media via dual 1:1 isolation transformers. No external
filter is required.
15.2.2.1 Clock Selection
The PHY has an on-chip crystal oscillator which can also be driven by an external oscillator. In this
mode of operation, a 25-MHz crystal should be connected between the XTLPPHY and XTLNPHY
pins. Alternatively, an external 25-MHz clock input can be connected to the XTLP pin. In this mode
of operation, a crystal is not required and the XTLN pin must be tied to ground.
15.2.2.2 Auto-Negotation
The PHY supports the auto-negotiation functions of Clause 28 of the IEEE 802.3 standard for 10/100
Mbps operation over copper wiring. This function can be enabled via register settings. The
autonegotiation function defaults to On and bit 12 (ANEGEN) in the MR0 register is High after reset.
Software can disable the auto-negotiation function by writing to the ANEGEN bit. The contents of the
MR4 register are sent to the PHY’s link partner during auto-negotiation via fast-link pulse coding.
Once auto-negotiation is complete, bits 11:10 (DPLX and RATE) in the MR18 register reflect the
actual speed and duplex that was chosen. If auto-negotiation fails to establish a link for any reason,
bit 12 (ANEGF) in the MR18 register reflects this and auto-negotiation restarts from the beginning.
Writing a 1 to bit 9 (RANEG) in the MR0 register also causes auto-negotiation to restart.
15.2.2.3 Polarity Correction
The PHY is capable of either automatic or manual polarity reversal for 10BASE-T and auto-negotiation
functions. Bits 4 and 5 (RVSPOL and APOL) in the MR16 register control this feature. The default is
automatic mode, where APOL is Low and RVSPOL indicates if the detection circuitry has inverted
the input signal. To enter manual mode, APOL should be set High and RVSPOL then controls the
signal polarity.
15.2.2.4 MDI/MDI-X Configuration
The PHY supports the automatic MDI/MDI-X configuration as defined in IEEE 802.3 2002. This
eliminates the need for cross-over cables when connecting to another devices, such as a hub. The
algorithm is controlled via settings in the MR24 register. Refer to page 406 for additional details about
these settings.
15.2.2.5 LED Indicators
The PHY supports two LED signals that can be used to indicate various states of operation of the
Ethernet Controller. These signals are mapped to the LED0 and LED1 pins. By default, these pins
are configured as GPIO signals (PF3 and PF2). For the PHY layer to drive these signals, they must
be reconfigured to their hardware function. Refer to the GIPO chapter for additional details. The
June 14, 2007
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