LM3S2965 Datasheet, PDF (87/542 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2965 Microcontroller
Register 14: Device Capabilities 1 (DC1), offset 0x010
This register is predefined by the part and can be used to verify features. The PWM, SARADC0,
MAXADCSPD, WDT, SWO, SWD, and JTAG bits mask the RCGC0, SCGC0, and DCGC0 registers.
Other bits are passed as 0. MAXADCSPD is clipped to the maximum value specified in DC1.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
CAN1 CAN0
reserved
PWM
reserved
SARADC0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SYSDIV
MAXADCSPD
MPU
HIB TEMPSNS PLL
WDT SWO SWD JTAG
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
Bit/Field
31:26
25
24
23:21
20
19:17
16
15:12
Name
reserved
CAN1
CAN0
reserved
PWM
reserved
SARADC0
SYSDIV
Type
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
1
1
0
1
0
1
0x3
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
When set, indicates that CAN unit 1 is present.
When set, indicates that CAN unit 0 is present.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
When set, indicates that the PWM module is present.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
When set, indicates that general SAR ADC 0 is present.
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Value Description
0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4.
11:8
MAXADCSPD
RO
0x3
This field indicates the maximum rate at which the ADC samples data.
Value Description
0x3 1M samples/second
7
MPU
RO
1
When set, indicates that the Cortex-M3 Memory Protection Unit (MPU)
module is present. See the ARM Cortex-M3 Technical Reference Manual
for details on the MPU.
June 04, 2007
87
Preliminary