LM3S2965 Datasheet, PDF (78/542 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
Bit/Field
19:17
16:14
13
12
11
10
9:6
Name
PWMDIV
reserved
PWRDN
reserved
BYPASS
reserved
XTAL
Type
R/W
RO
R/W
RO
R/W
RO
R/W
Reset
0x7
Description
PWM Unit Clock Divisor
This field specifies the binary divisor used to predivide the system clock
down for use as the timing reference for the PWM module. This clock
is only power 2 divide and rising edge is synchronous without phase
shift from the system clock.
Binary Value Divisor
000
/2
001
/4
010
/8
011
/16
100
/32
101
/64
110
/64
111
/64 (default)
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL.
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
PLL Bypass
Chooses whether the system clock is derived from the PLL output or
the OSC source. If set, the clock that drives the system is the OSC
source. Otherwise, the clock that drives the system is the PLL output
clock divided by the system divider.
Note:
The ADC must be clocked from the PLL or directly from a
14-MHz to 18-MHz clock source to operate properly. While
the ADC works in a 14-18 MHz range, to maintain a 1 M
sample/second rate, the ADC must be provided a 16-MHz
clock source.
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0xB
This field specifies the crystal value attached to the main oscillator. The
encoding for this field is provided in Table 6-3 on page 79.
78
June 04, 2007
Preliminary